Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 33
3 Register Descriptions
The MCH contains two sets of software accessible registers, accessed via the Host processor I/O
address space:
• Control registers – These registers are mapped into the processor I/O space, and control access
to PCI configuration space (see Section 3.3, “I/O Mapped Registers” on page 3-38).
• Internal configuration registers – These registers, which reside within the MCH, are
partitioned into multiple logical device register sets (“logical” since they reside within a single
physical device). One register set is dedicated to Host-Hub Interface (HI) Bridge functionality
(controls PCI_A, DRAM configuration, other MCH operating parameters and optional
features). Another register set is dedicated to the internal DMA controller. Additional sets of
registers map to the virtual PCI-to-PCI bridges for the PCI Express ports.
The MCH internal registers (I/O Mapped and Configuration registers) are accessible by the host
processor. The registers can be accessed as Byte (8-bit), Word (16-bit), or Dword (32-bit)
quantities, with the exception of the CONFIG_ADDRESS register, which can only be accessed as
a Dword. All multi-byte numeric fields use “little-endian” ordering (i.e., lower address bits contain
the least significant parts of the field).
3.1 Register Terminology
Type Description
RO Read Only – Software/BIOS can only read registers/bits with this attribute. Contents are either
hardwired or set by hardware. Attempted Writes to RO locations have no effect.
WO Write Only – Attempted Reads of registers/bits with this attribute do not return valid data. Writes
to these locations cause some hardware event to take place.
R/W Read / Write – Software/BIOS can read and write to registers/bits with this attribute.
R/WC Read / Write Clear – Software/BIOS can read and write to registers/bits with this attribute.
However, writing a value of 0 to a bit with this attribute has no effect. A R/WC bit can only be set
to a value of 1 by a hardware event. To clear a R/WC bit (i.e., change the value to ‘0’), a value of
1 must be written to the bit location.
R/WS Read / Write Set – Software/BIOS can read and write to registers/bits with this attribute.
However, writing a value of 0 to a bit with this attribute has no effect. Software can set a R/WS
bit by writing a value of 1 to the location, but the bit can only be cleared to ‘0’ by hardware.
R/W/L Read / Write / Lock – Software/BIOS can read and write to registers/bits with this attribute.
Hardware or some other configuration bit can lock a R/W/L bit and prevent it from being
updated.
R/WO Read / Write Once – Software/BIOS can read, but only write to a register/bit with this attribute
once after reset. It is a special form of R/W/L. Once a R/WO bit has been written, it is locked and
subsequent attempts to Write this bit will have no effect unless the system is reset.
Reserved
Bits
Some of the MCH registers described in this section contain reserved bits. These bits are
labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads,
software must use appropriate masks to extract the defined bits and not rely on reserved bits
being any particular value. On writes, software must ensure that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read, merged
with the new values for other bit positions and then written back. The software does not need to
perform read, merge, write operation for the configuration address register.
