Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 3
Contents
1 Introduction.......................................................................................................................17
1.1 Terminology .......................................................................................................................17
1.2 Reference Documentation .................................................................................................20
1.3 Intel
®
E7520 MCH System Architecture ............................................................................20
1.3.1 64-bit Intel
®
Xeon™ Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) ..................................................................20
1.3.2 Memory Subsystem.............................................................................................20
1.3.3 PCI Express* .......................................................................................................21
1.3.4 Hub Interface 1.5 .................................................................................................21
1.3.4.1 Intel
®
82801ER I/O Controller Hub 5 R (ICH5R) ...............................21
1.3.4.2 Intel
®
6300ESB ICH...........................................................................21
1.3.5 Intel
®
6700PXH 64-bit PCI Hub...........................................................................22
1.3.6 Platform Summary...............................................................................................22
2 Signal Description ............................................................................................................23
2.1 System Bus Interface Signals ............................................................................................23
2.2 DDR Interface A Signals....................................................................................................26
2.3 DDR Interface B Signals....................................................................................................27
2.4 DDR Interface Shared Signals...........................................................................................27
2.5 PCI Express Interface Port A Signals ................................................................................28
2.6 PCI Express Interface Port B Signals ................................................................................29
2.7 PCI Express Interface Port C Signals ................................................................................29
2.8 PCI Express Interface Shared Signals...............................................................................30
2.9 Hub Interface Signals.........................................................................................................30
2.10 Reset, Power, and Miscellaneous Signals.........................................................................30
3 Register Descriptions .......................................................................................................33
3.1 Register Terminology.........................................................................................................33
3.1.1 Platform Configuration.........................................................................................34
3.2 General Routing Configuration Accesses ..........................................................................35
3.2.1 Standard PCI Bus Configuration Mechanism ......................................................37
3.2.2 Logical PCI Bus 0 Configuration Mechanism ......................................................37
3.2.3 Primary PCI and Downstream Configuration Mechanism ...................................37
3.2.4 PCI Express Bus Configuration Mechanism........................................................37
3.3 I/O Mapped Registers........................................................................................................38
3.3.1 CONFIG_ADDRESS – Configuration Address Register .....................................38
3.3.2 CONFIG_DATA – Configuration Data Register...................................................39
3.4 PCI Express Enhanced Configuration Mechanisms .........................................................39
3.4.1 PCI Express Configuration Transaction Header..................................................40
3.4.2 Enhanced Configuration Memory Address Map..................................................40
3.5 MCH Control Registers (D0:F0).........................................................................................41
3.5.1 VID – Vendor Identification (D0:F0).....................................................................42
3.5.2 DID – Device Identification (D0:F0) .....................................................................42
3.5.3 PCICMD – PCI Command Register (D0:F0) .......................................................43
3.5.4 PCISTS – PCI Status Register (D0:F0)...............................................................43
3.5.5 RID – Revision Identification (D0:F0) ..................................................................45
3.5.6 SUBC – Sub-Class Code (D0:F0) .......................................................................45
3.5.7 BCC – Base Class Code (D0:F0) ........................................................................45
3.5.8 MLT – Master Latency Timer (D0:F0) .................................................................46
3.5.9 HDR – Header Type (D0:F0)...............................................................................46
3.5.10 SVID – Subsystem Vendor Identification (D0:F0) ...............................................46
3.5.11 SID – Subsystem Identification (D0:F0) ..............................................................46