Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 27
Signal Description
2.3 DDR Interface B Signals
2.4 DDR Interface Shared Signals
Table 2-3. DDR Channel_B Interface Signals
Signal Name Type Description
DDRB_DQ[63:0] I/O
SSTL-2
DDR Channel B Data Bus: The DDR data bus provides the data from
the DRAM devices.
DDRB_CB[7:0] I/O
SSTL-2
DDR Channel B Check Bits: These check bits are required to provide
ECC Support
DDRB_DQSP[17:0]
DDRB_DQSN[17:0]
(DDR2 Only)
I/O
SSTL-2
DDR Channel B Data Strobes: The DDR data strobes. Each data strobe
is used to strobe a set of four data signals. These signals function as
differential pairs for DDR2 technology only.
DDRB_CMDCLKP[3:0]/
DDRB_CMDCLKN[3:0]
O
CMOS
DDR Channel B Command CLOCK: The DDR command clocks used
by the DDR DRAMs to latch MA[13:0], BA[2:0], RAS#, CAS#, WE#,
CKE#, and CS# signals.
DDRB_RAS# O
CMOS
DDR Channel B Row Address Strobe: Used to indicate a valid row
address and open a row.
DDRB_CAS# O
CMOS
DDR Channel B Column Address Strobe: Used to indicate a valid
column address and initiate a transaction.
DDRB_BA[2:0] O
CMOS
DDR Channel B Bank Address: The DDR bank address signals. These
signals are outputs of the MCH and select which bank within a row is
selected.
DDRB_MA[13:0] O
CMOS
DDR Channel B Memory Address: The DDR memory address signals.
DDRB_WE# O
CMOS
DDR Channel B Write Enable: Used to indicate a write cycle.
DDRB_CS[7:0]# O
CMOS
DDR Channel B Chip Select: Used to indicate to which DRAM device
cycles are targeted.
DDRB_VREF I
Analog
DDR Channel B Voltage Reference: DDR Reference voltage input.
Table 2-4. DDR Interface Shared Signals
Signal Name Type Description
DDR_CRES0 I/O
Analog
DDR Compensation Resistor Return: Common return for DDR
interface compensation resistors on DDRSLWCRES and
DDRIMPCRES.
DDR_SLWCRES I/O
Analog
Compensation Resistor: Slew rate compensation for DDR interface
DDR_IMPCRES I/O
Analog
Compensation Resistor: Impedance compensation for DDR interface
DDRCKE[7:0] O
CMOS
DDR Clock Enable: Two operating modes exist.:
• Shared across channels in lock-step, where [7:0] correspond to the
rows as defined in the DRAM Row Boundary registers (two CKE
signals for each DIMM slot).
• Independent per channel, with one CKE for each DIMM slot.
DDRRES[2:1] I/O
Analog
DDR Resistor: Additional compensation resistors for DDR interface