262 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Electrical Characteristics
6.4 DC Characteristics
NOTE:
1. GTLREF is either HACVREF or HDVREF, depending on whether the input is an address or control signal, or
a data signal.
NOTES:
1. Note that these input voltages apply only when the signals are inputs to the MCH. When the signals are
inputs to the SDRAM, the SDRAM input voltage specifications apply.
2. Output voltage level extremes are specified with into a 30 ohm termination load to the DDR bus termination
voltage, and are guaranteed by design (not 100% tested) for DDR operation.
3. Maximum currents are specified into a 30 ohm termination load to the DDR bus termination voltage, and are
guaranteed by design (not 100% tested) for DDR operation.
Table 6-8. FSB Interface DC Characteristics
Symbol
Signal
Group
Parameter Min Nom Max Unit Notes
V
IL_H
(a), (c) Host AGTL+ Input Low Voltage
GTLREF –
0.10 x Vtt
V 1
V
IH_H
(a), (c) Host AGTL+ Input High Voltage
GTLREF +
0.10 x Vtt
V 1
V
OL_H
(a), (b) Host AGTL+ Output Low Voltage 0.4 V
V
OH_H
(a), (b) Host AGTL+ Output High Voltage Vtt - 0.1 Vtt V
R
TT
Host Termination Resistance 45 50 55
I
OL_H
(a), (b) Host AGTL+ Output Low 17 mA
I
L_H
(a), (c) Host AGTL+ Input Leakage Current 100 A
C
PAD
(a), (c) Host AGTL+ Input Capacitance 1 2.5 pF
HACVREF (d)
Host Address and Common Clock
Reference Voltage
0.98 x
Nominal
0.63 x Vtt
1.02 x
Nominal
V
HDVREF (d) Host Data Reference Voltage
0.98 x
Nominal
0.63 x Vtt
1.02 x
Nominal
V
Table 6-9. DDR SDRAM Interface DC Characteristics
(1)
Symbol
Signal
Group
Parameter Min Nom Max Unit Notes
V
IL(DC)
(h) DDR Input Low Voltage (DC)
DDRVREF
– 0.075
V 3
V
IH(DC)
(h) DDR Input High Voltage (DC)
DDRVREF
+ 0.075
V 3
V
IL(AC)
(h) DDR Input Low Voltage (AC)
DDRVREF
– 0.175
V 3
V
IH(AC)
(h) DDR Input High Voltage (AC)
DDRVREF
+ 0.175
V 3
V
OL
(h), (i) DDR Output Low Voltage 0 0.414 V 4
V
OH
(h), (i) DDR Output High Voltage 2.0 Vdd_DDR V 4
C
PIN
(h), (i) DDR Pin Capacitance 2.5 3.75 pF
I
OL
(h), (i) DDR Output Low Current 20.7 mA 5
I
OH
(h), (i) DDR Output High Current 18 mA 5
I
Leak
(h) Input Leakage Current 1 A
DDRVREF (k) DDR Reference Voltage
Vdd_DDR /
2
V
