260 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Electrical Characteristics
NOTES:
1. The DC min/max window describes the power supply behavior required at frequencies below 5 MHz. The AC
min/max window describes the power supply behavior required at frequencies from 5 MHz to 2 GHz.
2. The analog voltage is intended to be a filtered copy of the 1.5V core supply voltage.
3. DDR and DDR2 operation are mutually exclusive; thus the MCH will draw only one of these Idd currents in a
given design.
4. Idd_DDR x Vdd_DDR does not equal power dissipated in the MCH from the DDR rail. Most of the current
supplied by the Idd rail at max current draw is sourced out the memory signal pins at some voltage above
ground. See the memory interface DC chapters for details.
5. Total current drawn off the 1.5V rail is separated into current drawn by the VCC balls and the VCCEXP balls
as shown in the component ballout in the EDS.
6. Note that the VCCEXP balls should be inductively isolated from the VCC balls to avoid noise coupling from
the core onto the VCCEXP rail, which is particularly sensitive to AC noise.
6.3 I/O Interface Signal Groupings
VccA_SB
Vcca_HI
Vcca_EXP
Vcca_DDR
Analog Supply Voltages 1.406 1.5 1.545 V 2
Vcc_BG Analog Bandgap Voltage 2.425 2.5 2.575 V
V3REF V3REF Voltage 3.135 3.201 3.3 3.399 3.465 V
Table 6-2. Operating Condition Power Supply Rails (Sheet 2 of 2)
Symbol Parameter Minimum Nominal Maximum Unit Notes
Table 6-3. Signal Groups FSB Interface
Signal
Group
Signal Type Signals Notes
(a) AGTL+ I/O
AP [1:0]#, ADS#, BNR#, DBSY#, DEP[3:0]#, DRDY#, HA
[35:3]#, HADSTB [1:0] #, HD [63:0] #, HDSTBP [3:0]#,
HDSTBN [3:0]#, HIT#, HITM#, HREQ [4:0]#, BREQ[0]#,
DINV[3:0]#, MCERR#
(b) AGTL+ Output BPRI#, CPURST#, DEFER#, HTRDY#, RS [2:0]#, RSP#
(c) AGTL+ Input HLOCK#, BINIT#, BREQ[1]#
(d)
Host Reference Voltage
(Analog)
HDVREF [1:0], HACVREF
(e)
Host Compensation
(Analog)
HODTCRES, HSLWCRES, HCRES0
(f) Clock CMOS Inputs HCLKINN, HCLKINP
Table 6-4. Signal Groups Memory (DDR and DDR2) Interface (Sheet 1 of 2)
Signal
Group
Signal Type Signals Notes
(h) DDR and DDR2 I/O DDRx_DQ[63:0], DDRx_CB[7:0], DDRx_DQSP[17:0] 1
