256 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
5.12.3 Unsupported Access Addresses
It is possible for an SMBus master to program an unsupported bit combination into the ADDR
registers. The MCH does not support such usage, and may not gracefully terminate such accesses.
5.12.4 SMB Transaction Pictograms
Since the new SMB target interface is of enterprise origin, it is more complex than the original
SMB target interface of desktop origin. The following drawings are included which should be
better than words to demonstrate the different types of transactions, especially how they can be
broken up into multiple smaller transfers.
5
Internal Master Abort.
0 = No Internal Master Abort Detected.
1 = Detected an Internal Master Abort.
4
Internal Target Abort.
0 = No Internal Target Abort Detected.
1 = Detected an Internal Target Abort.
3:1 Ignored.
0
Successful.
0 = The last SMBus transaction was not completed successfully.
1 = The last SMBus transaction was completed successfully.
Position Description
Figure 5-14. DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
PEC Disabled)
Figure 5-15. DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled)
Figure 5-16. DWORD Memory Read Protocol (SMBus Block Write / Block Read, PEC Disabled)
S 0110_000 W A Cmd = 11000010 A
Sr
0110_000 R A Byte Count = 5 A Status A Data[31:24] A Data[23:16] A Data[15:8]
A Data[7:0]
S 0110_000 W A Cmd = 11000010 A Byte Count = 4 A Bus Number A Device/Function A Reg Number[15:0] A
Reg Number [7:0]
CLOCK STRETCH
A P
N P
A
S 0110_000 W A Cmd = 11001110 A Byte Count = 8
A Bus Number A Device/Function A Reg Number[15:8] A Reg Number [7:0] A Data[31:24]
Data[23:16] A Data[16:8] A Data[7:0] CLOCK STRETCH A P
S 0110_000 W A Cmd = 11100010 A Byte Count = 4 A Destination Mem A Add Offset[23:16] A Add Offset[15:8] A
S 0110_000 W A Cmd = 11100010 A
Sr
0110_000 R A Byte Count = 5 A Status A Data[31:24] A Data[23:16] A Data[15:8] A
Data[7:0]
N P
Add Offset[7:0] CLOCK STRETCH A P
