Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 253
Functional Description
Table 5-14 indicates the sequence of data as it is presented on the SMBUS following the byte
address of the MCH itself. This is not to necessarily indicate any specific register stack or array
implemented in the MCH. Note that the fields can take on different meanings depending on
whether it is a configuration or memory-mapped access type. The command indicates how to
interpret the bytes.
5.12.2.1 Command Field
The command field indicates the type and size of transfer. All configuration accesses from the
SMBus port are initiated by this field. While a command is in progress, all future writes or reads
will be NACK’d by the MCH to avoid having registers overwritten while in use. The two
command size fields allows for more flexibility on how the data payload is transferred, both
internally and externally. The begin and end bits support the breaking of the transaction up into
smaller transfers, by defining the start and finish of an overall transfer.
5 ADDR1
Extended Register Number (Register Mode) or Address Offset [15:8] (Memory
Mapped Mode)
6 ADDR0 Register Number (Register Mode) or Address Offset [7:0] (Memory Mapped Mode)
7 DATA3 Fourth Data Byte [31:24]
8 DATA2 Third Data Byte [23:16]
9 DATA1 Second Data Byte [15:8]
10 DATA0 First Data Byte [7:0]
11 STS Status, only for reads
Table 5-14. SMBus Transaction Field Summary (Sheet 2 of 2)
Position Mnemonic Field Name
Position Description
7
Begin Transaction Indicator.
0 = Current transaction is NOT the first of a read or write sequence.
1 = Current transaction is the first of a read or write sequence. On a single transaction sequence
this bit is set along with the End Transaction Indicator.
6
End Transaction Indicator.
0 = Current transaction is NOT the last of a read or write sequence.
1 = Current transaction is the last of a read or write sequence. On a single transaction sequence
this bit is set along with the Begin Transaction Indicator.
5
Address Mode. Indicates whether memory or configuration space is being accessed in this
SMBus sequence.
0 = Memory Mapped Mode
1 = Configuration Register Mode
4
Packet Error Code (PEC) Enable. When set, each transaction in the sequence ends with an
extra CRC byte. The MCH would check for CRC on writes and generate CRC on reads. PEC is
not supported by the MCH.
0 = Disable
1 = Not Supported