250 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
The signaling due to internally detected PCI Express errors has its logic dependent on the Device
Status register (Device 2-7, Function 0, Offset 6E-6Fh). The Device Status register must be cleared
before exiting the error service routine.
Software must clear the global FERR first, and then the global NERR. Software then clears the
local FERR register and the local NERR register of each unit in that order. After clearing FERR
and then clearing NERR, the local FERR should be read to make sure that remains ‘0’ indicating
no more errors have occurred during the clearing of these registers. After all units’ FERR & NERR
registers have been cleared, the global FERR is again read to ensure that no additional errors
occurred during the clearing sequence.
Since the PCI Express units have more hierarchy than other units, more registers must be cleared
other than just the local FERR and NERR registers. After clearing the local FERR & NERR, one
must also clear the Root Error Status, Unit Error Status, Device Status, Uncorrectable Error Status,
and Correctable Error Status registers. One only needs to clear the PCI Status and Secondary Status
registers if these are being utilized in a given particular error model. No logic depends on the state
of any of these status bits. If not utilized, they can be ignored.
If a PCI Express error handler is used, with no knowledge of the FERR/NERR registers, then clear
the PCI Express-specific registers: Device Status, Uncorrectable Error Status, Correctable Error
Status, and Root Error Status. The MCH specific unit errors would not be enabled for reporting
errors.
Figure 5-13. PCI Express Error Handling
Uncorrectable Error Mask
UNCERRMSK
Correctable Error Status
CORERRSTS
Correctable Error Mask
CORERRMSK
Uncorrectable Severity
UNCERRSEV
Enable
SysERR
Mask on a
per bit basis
Fatal
Message
Uncorrectable
Errors
Correctable
Errors
Correctable
Message
Non-fatal
Message
Device Status
HSIDEVSTS
Device Control
HSIDEVCTL
3GIO Base
registers in
blue
PCICMD[8]
Mask on a
per bit basis
Virtual Correctable
Message
Virtual Non-fatal
Message
Adv. Error Capability &
Control
AERCACR
Header Log Register
HDRLOG[3:0]
Uncorrectable Error Status
UNCERRSTS
This set of white registers
compromise the advanced
error reporting structure for
HSI
Uncorrectable Emask Correctable Emask
Uncorrectable Severity
UNCERRSEV
All UNCs
Root Error Status
RPERRMSTS
Error Source ID
ERRSID
REPORT SELECT
DESIGN SPECIFIC
BERR
SCI
SMI
MSI
INTx
Root
Control
report enable
1
st
Error
Indicators
1
st
Error
Source IDs
HSIRPCTL
HSIERR
DOCMD
Design specific
registers in dark grey
SERR
Correctable Error Ptr
HSIERRDOCMD
NFM
FM
BCTRL[1]
SERRE
Virtual &
Recieved
Message
Logic
SECSTS[14]
RSE
All UNCs
Unsupport Request
UR
[3]
PCISTS[14]
SSE
F NF C
UNCs
w/o UR
MSICAPA
[0]
Root Error Cmd
Irpt Enable per type
Root Error Cmd
Irpt Enable per type
RPERRCMD
RPERRCMD
MSI enable
