Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 249
Functional Description
or unsupported) reporting is enabled in the Device Control register (Device 2-7, Function 0, Offset
6Ch) bits 3:0. Finally, uncorrectable error reporting (fatal or non-fatal) reporting may also be
enabled by setting the SERR Enable bit in the PCI Command register (Device 2-7, Function 0,
Offset 04-05h).
There is an error pointer, in the Advanced Error Capability and Control register (Device 2-7,
Function 0, Offset 118-11Bh) which will log the first uncorrectable error that is enabled for
reporting. Also some uncorrectable errors, when they are the first uncorrectable error, will log their
corresponding header log in the Header Log registers (Device 2-7, Function 0, Offset 11C-12Bh).
An error pointer for unmasked correctable errors has been added in the Error Do Command register
(Device 2-7, Function 0, Offset 148-14Bh).
These internally detected errors when they are reported are referred to as virtual error messages.
These are different from errors which are detected by the downstream device which then sends an
error message to the root complex, which are referred to as externally detected or “received’ error
messages. The received system error bit in the PCI Secondary Status register (Device 2-7, Function
0, Offset 1E-1F) is set when either fatal or non-fatal messages are received at the root complex.
At this point in the PCI Express error hierarchy, these virtual error messages are logically OR’ed
with the received error messages, and will just be referred to as fatal, non-fatal, or correctable error
messages, no reference to either virtual or received.
When enabled by the enable system error bit in the PCI Command register, any fatal or non-fatal
messages will set the signaled system error bit in the PCI Status register (Device 2-7, Function 0,
Offset 06-07h). The Root Port Error Message Status register (Device 2-7, Function 0, Offset
130-133h) will indicate first and multiple errors of each error message category, and the
corresponding error source IDs of the first correctable and uncorrectable error messages will be the
logged in the Root Port Error Source ID register (134h).
These errors that have been reported to the root complex can now be reported to the system, via the
category enables in the Root Port Error Command register (Device 2-7, Function 0, Offset
12C-12Fh) for interrupts. These interrupts can be in the form of legacy type interrupts if so enabled
in the PCI command register and MSI is not enabled, or message signaled interrupts if so enabled
in the MSI Capabilities register (Device 2-7, Function 0, Offset 5A-5Bh).
The Root Port Control register (Device 2-7, Function 0, Offset 80-83h) enables errors to be
reported to the system via other MCH specific methods, again on a category basis. The Error Do
Command register, selects between the four methods of system signaling, SERR, SCI, SMI, and
MCERR.
The error model outside of PCI Express includes a local FERR/NERR pair of registers in each unit
and a global FERR/NERR pair of registers that indicates which unit had problems. The Local
FERR/NERR register pair (Device 2-7, Function 0, Offset 160-163h & 164-167h) includes PCI
Express defined errors and additional detected errors within the PCI Express unit. This register
pair has three sets of error bits for the three categories of errors: the first set for received messages,
the second set for internally detected errors (virtual messages need not have been generated), and
unit specific errors outside of the PCI Express Specification, and the third set for device errors. The
error scheme sets FERR/NERR error bits regardless whether or not they were reported via interrupt
or other signaling method.
The signaling due to unit specific errors has its logic dependent on the PCI Express Unit Error
register (Device 2-7, Function 0, Offset 140-143h). The errors flagged in this register must be
cleared before exiting the error service routine.
The signaling due to received messages has its logic dependent on the Root Error Status register
(Device 2-7, Function 0, Offset 130-133h). The Root Error Status register must be cleared before
exiting the error service routine.
