Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 243
Functional Description
It is up to the platform designer to ensure that the power management controller can adequately
isolate the source of a PME wake request as required to take appropriate power management
wake-up action.
5.9.6.3 In-Band PCI Express Wake Mechanism
The PCI Express In-Band Wake Mechanism is not supported by this MCH.
5.9.6.4 PME Messaging
Once the link requesting a power state change has a communicative upstream link, it sends the
PM_PME packet upstream towards the root device (MCH), which in turn is responsible for
notifying the management controller. This constitutes an in-band “virtual wire” signaling
mechanism to replace the historical solution that involved multiple independent board traces
routing PME requests to the power manager. Because the PM_PME propagates “in-band” on the
PCI Express interface without any sideband signaling support, PME functionality is made available
to multi-chassis system solutions.
The MCH will collect PME requests from all logical PCI Express ports, and forward a single
MCHPME# output signal directly to the PME# input of the ICH reserved for power management
events. The ICH will then generate a specified interrupt to wake the power manager, and invoke
power management software. The interrupt service routine may then interrogate the various PM
status registers to determine the source(s) of PME. Note that the ICH PME# pin utilized for PME
signaling may not be shared by any other runtime function within the platform.
5.9.6.5 Limitations and Exceptions for Legacy PME
The PME messaging support just outlined for the MCH-based platform is rather inelegant, in that
very little information is available to the power management controller. There are further
limitations in terms of both lost and spurious PME events as a result of imperfect translation
between the PCI Express in-band “virtual wire” PME mechanism, and the sideband level-sensitive
physical wire from MCH to power manager.
This state of affairs is necessitated by the lead intercept nature of a MCH, where the MCH is PCI
Express-aware prior to availability of similarly aware ICH and power management control devices.
Mechanisms are provided within the PCI Express PME semantic to render both spurious and lost
PME messages benign from a system architecture perspective.
5.9.7 BIOS Support for PCI Express PM Messaging
The PCI Express Interface Specification, Rev 1.0a stipulates hierarchical messaging semantics
enforced by the root device (the MCH) to guarantee proper entry into and exit from unpowered
device states. The MCH ACPI BIOS must make special allowances for support of these semantics
due to the lack of PCI Express-aware ICH and power management devices in MCH-based
platforms. There are two sets of messages that must be software-assisted in MCH-based platforms
to support power-off device states within the PCI Express hierarchy.
5.9.7.1 PCI Express PME_TURN_OFF Semantic
Prior to removing power from any attached PCI Express links anywhere in the hierarchy, the root
device must broadcast a PCI Express “PME_TURN_OFF” message to all downstream devices on
the affected PCI Express port. The receiving devices will propagate this message to all subordinate
PCI Express ports (if any), collect “PME_TO_ACK” acknowledgement packets, and finally return
a “PME_TO_ACK” transaction layer packet back to the root device. Once all active ports have
