Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 241
Functional Description
5.9.5.3 System Clocking Solution Dependencies
The topology of the platform clocking solution will dictate the viability of ASPM on each of the
PCI Express links, because the nature of the clocks directly impacts the amount of time required to
reacquire bit and symbol lock in the receiver after an arbitrarily long non-communicative period.
When both ends of a link share a clock source, they will “wander” together over the period they are
out of communication with each other, and accordingly will require a relatively brief period of
training to reacquire lock. When the two ends of a link utilize completely independent clock
references, they may become arbitrarily out of phase with each other while they are in low power
states, and will therefore require a significantly longer amount of time to reacquire lock upon
waking. For this reason, the PCI Express Interface Specification, Rev 1.0a provides for software
discovery and communication of the actual clocking topology within the system prior to enabling
the ASPM feature on any link within the system.
There are two primary components to the clocking discovery mechanism. Firstly all downstream
ports, such as those on the MCH root device, must report whether they use the same clock source
as that provided to the slot (or down-device) connected to that port in the platform. This
information is recorded in the Slot Clock Configuration bit of the Link Status register for each port,
and system BIOS is required to initialize these bits accordingly. Secondly, all add-in devices must
report whether they utilize the clock reference provided on the add-in slot via the same bit in the
same register of their capability structure.
System software may examine the settings of the Slot Clock Configuration bits of both the
upstream and downstream devices for each port in the system, and determine whether a common
clock reference is in use. This information is then communicated to both the upstream and the
downstream devices via programming of the Common Clock Configuration bit of the Link Status
register. The setting of this bit determines the reported exit latency requirements for the L0s and L1
states. System software may then compare the exit latency requirements with the tolerated exit
latencies of the attached device, and determine whether or not to enable ASPM for each link the
system. (All ASPM functionality defaults to disabled at power-on, and will remain so unless
system software determines it may be enabled.)
Note that the “N_FTS” parameters exchanged during initial training will correspond to the “long”
exit latencies associated with independent clocks, so if software later sets the Common Clock
Configuration bits, it is also necessary to force link retraining in order to update the exchanged
N_FTS information.
5.9.5.4 Device and Link PM Initialization
All PCI Express devices will power-on into the D0 uninitialized state, and will remain in that
non-communicative state until they have been configured and at least one of the Memory Space
Enable, I/O Space Enable, or Bus Master Enable bits has been set by system software, at which
point the device will automatically transition to the D0 active state indicative of normal operation.
5.9.5.5 Device and Slot Power Limits
All add-in devices must power-on to a state in which they limit their total power dissipation to a
default maximum according to their form factor (10W for add-in edge-connected cards). When
BIOS updates the slot power limit register of the root ports within the MCH, the MCH will
automatically transmit a Set_Slot_Power_Limit message with corresponding information to the
attached device. It is the responsibility of platform BIOS to properly configure the slot power limit
registers in the MCH, and failure to do so may result in attached endpoints remaining completely
disabled in order to comply with the default power limitations associated with their form factors.
