24 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Signal Description
BNR# I/O
AGTL+
Block Next Request: Used to block the current request bus owner from
issuing new requests. This signal is used to dynamically control the
system bus pipeline depth.
BPRI# O
AGTL+
Priority Agent Bus Request: The MCH is the only Priority Agent on the
system bus. It asserts this signal to obtain the ownership of the address
bus.
The MCH has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal is asserted.
BREQ0# I/O
AGTL+
Bus Request 0#: The MCH pulls the processor bus BREQ0# signal low
during CPURST#. The signal is sampled by the processors on the active-
to-inactive transition of CPURST#. The minimum setup time for this
signal is 4 HCLKs.
BREQ1# I
AGTL+
Bus Request 1#: The MCH does not drive this pin. It is used by the
processors for symmetric bus arbitration. The MCH samples this signal
during run time only.
CPURST# O
AGTL+
Processor Reset: The MCH asserts CPURST# while RSTIN#
(PCIRST# from ICH) is asserted and for approximately 1 ms after
RSTIN# is deasserted. The CPURST# allows the processors to begin
execution in a known state.
DBSY# I/O
AGTL+
Data Bus Busy: Used by the data bus owner to hold the data bus for
transfers requiring more than one cycle.
DEFER# O Defer: Signals that the MCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.
DEP[3:0]# I/O
AGTL+
Host Data Parity: The DEP[3:0]# signals provide parity protection for
HD[63:0]#. The DEP[3:0]# signals are common clock signals and are
driven one common clock after the data phases they cover. DEP[3:0]#
are driven by the same agent driving HD[63:0]#.
Data parity is correct if there are an even number of electrically low
signals (low voltage) in the set consisting of the covered signals plus the
parity signal.
DBI[3:0]# I/O
AGTL+
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.
Indicates when the associated signals are inverted. DBI[3:0]# are
asserted such that the number of data bits driven electrically low (low
voltage) within the corresponding 16-bit group never exceeds eight.
DRDY# I/O
AGTL+
Data Ready: Asserted for each cycle that data is transferred.
HA[35:3]# I/O
AGTL+
2x
Host Address Bus: HA[35:3]# connect to the system address bus.
During processor cycles, HA[35:3]# are inputs. The MCH drives
HA[35:3]# during snoop cycles on behalf of Hub Interface (HI) initiators.
HACVREF I Host Address/Control and Common Clock Bus Reference Voltage:
Reference voltage input for the Address and Control signals of the Host
AGTL+ interface.
HADSTB[1:0]# I/O
AGTL+
2x
Host Address Strobe: The source synchronous strobes are used to
transfer HA[35:3]# and HREQ[4:0]# at the 2x transfer rate.
HCLKINN
HCLKINP
I
CMOS
Differential Host Clock In: These pins receive a differential host clock
from the external clock synthesizer. This clock is used by all the MCH
logic in the host clock domain.
HCRES0 I/O
Analog
Host Compensation Resistor Return: Common return for host bus
compensation resistors on HODTCRES and HSLWCRES.
HD[63:0]# I/O
AGTL+
4x
Host Data: These signals are connected to the system data bus.
Table 2-1. System Bus Signal Description (Sheet 2 of 4)
Signal Name Type Description
