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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 239
Functional Description
5.9.3 DDR Interface Power Management
Hardware in the MCH detects idle conditions on a per-chip-select basis on the DDR subsystem,
and places the idle DIMM (or DIMM rank) in a clock-disabled low-power state. When in
dual-channel operating mode, the MCH simultaneously executes identical control on the
corresponding chip selects and clock enables across the two channels. This is true also for the
power saving feature described here, because a two-channel configuration necessarily runs in
lock-step. When a new access decodes to a sleeping chip select, a single extra clock of latency is
incurred to re-enable the clock prior to issuing an activate cycle.
This power saving feature is above and beyond any software power management, and need only be
enabled by system BIOS or firmware. No further software direction or interaction is required to
realize the power savings from this feature.
No support is provided for self-refresh in the memory subsystem for this dynamic
hardware-managed mechanism, thus the idled DRAM devices will be dynamically awakened for
refresh operations, and subsequently put back to sleep provided the idle condition persists.
5.9.4 PCI Express Interface Power Management
In PCI Express, the traditional bus (B*) power states assigned to system buses are replaced by link
(L*) power states, which are largely managed by hardware without software intervention. Entry
into and out of these states may be initiated by two distinct mechanisms: traditional PCI-PMI type
software managed state changes, and non-traditional PCI Express autonomous hardware state
changes. The latter transition type is designated “Active State Power Management,” (ASPM) and is
new with the PCI Express Interface Specification, Rev 1.0a.
5.9.5 PCI Express Link Power State Definitions
The PCI Express Specification defines the following PCI Express link power states:
L0 – Active state with all operations enabled (default state after platform initialization)
L0s – Low latency, energy saving standby state, disabling exchange of both transaction layer
packets and device link layer messages. This state is used exclusively by the ASPM PCI
Express function, with entry and exit managed autonomously by PCI Express interface
hardware. Transitions into and out of the L0s state are accomplished with latencies under 4 ms.
L1 – Moderate to high latency, very low power, standby state, disabling exchange of both
transaction layer packets and device link layer messages. Entered when the downstream device
is programmed to a device power state below the D0 active state, or optionally under hardware
control during ASPM. The clock remains active in L1, and exit from this state may be initiated
by either the upstream or the downstream device.
L2/L3 Ready – Staging point for removal of main power and clocking. New intermediate state
not directly related to PCI PM D-state transitions, nor to ASPM. Hand-shaking will land the
link in this state in anticipation of power removal, at which point the link will move to either
L2 or L3 depending upon the presence of Vaux.
L2 – High latency, very low deep sleep state, disabling exchange of transaction layer packets
and device link layer messages. L2 is characterized by removal of clocking and main power,
but presence of Vaux power. Exit is initiated by restoring clocking and power, and full
initialization.
L3 – High latency, link off state with power, Vaux, and clock reference removed. Exit is
initiated by restoring clocking and power, and full initialization.
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