Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 237
Functional Description
case of a power-on sequence, the MCH internal “hard” and “core” resets de-assert simultaneously.
The two lines marked with names beginning “HLA” illustrate the Hub Interface special cycle
handshake between the MCH and the ICH to coordinate across the de-asserting edge of the
CPURST# output from the MCH.
Table 5-12 summarizes the durations of the various reset stages illustrated above, and attributes the
delays to the component that enforces them.
The fixed delays provide time for subordinate PLL circuitry to lock on interfaces where the clock is
withheld or resynchronized during the reset sequence.
5.9 Platform Power Management Support
The MCH is compatible with the PCI Bus Power Management Interface Specification, Rev 1.1
(referred to here as PCI-PMI). It is also compatible with the Advanced Configuration and Power
Interface Specification (ACPI). The MCH is designed to operate seamlessly with operating systems
employing these specifications.
Figure 5-11. Power-On Reset Sequence
Table 5-12. Reset Sequences and Durations
From To Duration Source Comment
Power on PwrGd >2mS Platform
Control logic on the platform must ensure that there are
at least 2mS of stable power before PwrGd is asserted.
PwrGd
RSTIN#
deassertion
1mS ICH
ICH enforces delay between detecting PwrGd asserted
and releasing PCIRST# (note that ICH PCIRST# is
directly connected to MCH RSTIN#).
RSTIN#
deassertion
Hard/Core
deassertion
4-6 HCLK MCH
MCH waits for a common rising edge on all internal
clocks, then releases core reset(s).
RSTIN#
deassertion
CPURST#
deassertion
1mS MCH
MCH enforces delay between RSTIN# and CPURST#
deassertion. Hublink handshake is incremental to the
timer.
HCLK
RSTIN#
Hard_Reset
Core_Reset
HLA_rstdonecomp
CPURST#
4-6 HCLK
1 mS
HLA_cpurstdone
PwrGd
Cold_Reset
1 mS
