236 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
have completed. After clearing bit 6, software may determine when the downstream targeted reset
has effectively completed by monitoring the state of bit 1 (Link Active) of the VS_STS1 register
(offset 47h) in the target root port device. This bit will remain deasserted until the link has regained
“link up” status, which implies that the downstream device has completed any internal and
downstream resets, and successfully completed a full training sequence.
Under normal operating conditions it should not be necessary to initiate targeted resets to
downstream devices, but the mechanism is provided to recover from combinations of fatal and
uncorrectable errors which compromise continued link operation.
5.8.1.5 BINIT# Mechanism
The BINIT# mechanism is provided to facilitate processor handling of system errors which result
in a hang on the FSB. MCA code responding to an error indication (typically IERR# or MCERR#)
will attempt to interrogate the MCH for error status, and if that FSB transaction fails to complete
the processor will automatically time out and respond by initiating a BINIT# sequence on the FSB.
When BINIT# is asserted on the FSB, all agents (the MCH and all CPUs) are required to reset their
internal FSB arbiters and all FSB tracking state machines and logic to their default states. This will
effectively “un-hang” the bus to provide a path into chipset configuration space. Note that the
MCH and PXHs implement “sticky” error status bits, providing the platform software architect
with free choice between BINIT# and a general hard reset to recover from a hung system.
Although BINIT# will not clear any configuration status from the system, it is not a recoverable
event from which the platform may continue normal execution without first running a hard reset
cycle. To guarantee that the FSB is cleared of any hang condition, the MCH will clear all pending
transaction state within its internal traffic structures. This applies to outstanding FSB cycles as
required, but also to in-flight memory transactions and inbound transactions. The resulting state of
the platform will be highly variable depending upon what precisely got wiped-out due to the
BINIT# event, and it is not possible for hardware to guarantee that the resulting state of the
machine will support continued operation. What the MCH can guarantee is that no subordinate
device has been reset due to this event (PCI Express links remain “up”), and that no internal
configuration state (sticky or otherwise) has been lost. The MCH will also continue to maintain
main memory via the refresh mechanism through a BINIT# event, thus machine-check software
will have access not only to machine state, but also to memory state in tracking-down the source of
the error.
5.8.2 Power Sequencing Requirement
There are 3.3V decoupling structures in the miscellaneous I/O pads which create a parasitic diode
path that will be forward-biased if the core 1.5V supply is brought up while the 3.3V supply
remains at ground. For this reason, the 3.3V supply must be brought up before the 1.5V core
supply, or at least the 3.3V supply must not be allowed to get more than 0.5V below the level of the
1.5V core supply. This sequencing requirement must also be enforced when the two supplies are
ramping down as they shut off.
5.8.3 Reset Sequencing
Figure 5-11 contains a timing diagram illustrating the progression through the power-on reset
sequence. This is intended as a quick reference for system designers to clarify the requirements of
the MCH.
Note the breaks in the clock waveform at the top of Figure 5-11, which are intended to illustrate
further elapsed time in the interest of displaying a lengthy sequence in a single picture. Each of the
delays in the reset sequence is of fixed duration, enforced by either the MCH or the ICH. In the
