Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 235
Functional Description
The PCI Express attached devices and any hierarchy of components underneath them are held in
reset via implicit messaging across the PCI Express interface. The MCH is the root of the
hierarchy, and will not engage in link training until power is good, the internal “hard” reset has
deasserted, and the port has been turned on.
A PwrGd reset will clear all internal state machines and logic, and initialize all registers to their
default states, including “sticky” error status bits that are persistent through all other reset classes.
To eliminate potential system reliability problems, all devices are also required to either tri-state
their outputs or to drive them to “safe” levels during a power-on reset.
The only system information that will “survive” a PwrGd reset is battery-backed or otherwise
non-volatile storage (Flash, ROM, PROM, etc.).
5.8.1.2 Hard Reset Mechanism
Once the platform has been booted and configured, a full system reset may still be required to
recover from system error conditions related to various device or subsystem failures. The “hard”
reset mechanism is provided to accomplish this recovery without clearing the “sticky” error status
bits useful to track down the cause of system reboot.
A hard reset is typically initiated by the ICH via the PCIRST# output pin, which is commonly
connected directly to the MCH RSTIN# input pin. The ICH may be caused to assert PCIRST# via
both software and hardware mechanisms. Refer to the Intel
®
82801ER I/O Controller Hub 5 R
(ICH5R) Datasheet for details. The MCH will recognize a hard reset any time RSTIN# is asserted
while PwrGd remains asserted.
The MCH will propagate a hard reset to the FSB and to all subordinate PCI Express subsystems.
The FSB components are reset via the CPURST# signal, while the PCI Express subsystems are
reset implicitly when the root port links are taken down.
A hard reset will clear all internal state machines and logic, and initialize all “non-sticky” registers
to their default states. Note that although the error registers will remain intact to facilitate
root-cause of the hard reset, the MCH platform in general will require a full configuration and
initialization sequence to be brought back on-line (all other volatile configuration information is
lost).
5.8.1.3 Processor-Only Reset Mechanism
For power management and other reasons, the MCH supports a targeted processor only reset
semantic. This mechanism was added to the platform architecture to eliminate double-reset to the
system at large when reset-signaled processor information (such as clock gearing selection) must
be updated during initialization bringing the system back to the S0 state after power had been
removed from the processor complex.
5.8.1.4 Targeted Reset Mechanism
The targeted reset is provided for Hot-Swap events, as well as for port-specific error handling
under MCA or SMI software control. The former usage model is new with PCI Express*
technology, and the reader is referred to the PCI Express Interface Specification, Rev 1.0a for a
description of the Hot-Swap mechanism.
A targeted reset may be requested by setting bit 6 (Secondary Bus Reset) of the Bridge Control
register (offset 3Eh) in the target root port device. This reset will be identical to a general hard reset
from the perspective of the destination PCI Express device; it will not be differentiated at the next
level down the hierarchy. Sticky error status will survive in the destination device, but software will
be required to fully configure the port and all attached devices once reset and error interrogation
