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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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234 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
The MCH can tolerate a non-SSC PCI Express subsystem, where multiple endpoints receive
independent and potentially differing reference frequencies. However, the MCH cannot tolerate a
“split personality” PCI Express subsystem. Either all PCI Express endpoints utilize the same
reference as the MCH, and SSC may be enabled; or all PCI Express endpoints are assumed to be
independent, and the entire PCI Express subsystem must operate without SSC. (It is strictly
prohibited to create a configuration in which the two ends of any given PCI Express link receive
independent SSC enabled reference clocks.)
5.8 System Reset
The MCH is the root of the I/O subsystem tree, and is therefore responsible for general propagation
of system reset throughout the platform. The MCH must also facilitate any specialized
synchronization of reset mechanisms required by the various system components.
5.8.1 MCH Reset Types
The MCH differentiates among five types of reset as defined in table Table 5-11.
5.8.1.1 Power-Good Mechanism
The initial boot of a MCH platform is facilitated by the Power-Good mechanism. The voltage
sources from all platform power supplies are routed to a system component which tracks them as
they ramp-up, asserting the platform PwrGd” signal a fixed interval (nominally 2mS) after the last
voltage reference has stabilized.
Both the MCH and the ICH receive the system PwrGd signal via dedicated pins as an
asynchronous input, meaning that there is no assumed relationship between the assertion or
deassertion of PwrGd and any system reference clock. When PwrGd is deasserted all platform
subsystems are held in their reset state. This is accomplished by various mechanisms on each of the
different interfaces. The MCH will hold itself in a power-on reset state when PwrGd is deasserted.
The ICH is expected to assert its PCIRST# output and maintain its assertion for 1mS after power is
good. The PCIRST# output from ICH is expected to drive the RSTIN# input pin on the MCH,
which will in turn hold the processor complex in reset via assertion of the CPURST# FSB signal.
Table 5-11. MCH Reset Classes
Type Mechanism Effect / Description
Power-Good PwrGd input pin
Propagated throughout the system hierarchy. Resets all logic and
state machines, and initializes all registers to their default states
(sticky and non-sticky). Tri-states all MCH outputs, or drives them to
“safe” levels.
Hard
RSTIN# input pin,
Configuration Write
Propagated throughout the system hierarchy. Resets all logic and
state machines, and initializes all non-sticky registers to their default
states. Tri-states all MCH outputs, or drives them to “safe” levels.
Processor-only Configuration Write
Propagated to all processors via the CPURST# pin on the FSB. The
MCH does not undergo an internal reset.
Targeted Configuration Write
Propagated down the targeted PCI Express port hierarchy. Treated
as a “Hard” reset by all affected components, clearing all machine
state and non-sticky configuration registers.
BINIT#
Internal error handling
propagated via FSB
BINIT# pin
Propagated to all FSB attached components (the MCH and up to
two processors). Clears the IOQ, and resets all FSB arbiters and
state machines to their default states. Not recoverable.
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