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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
232 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
5.5.5 PCI Express Retrain
If the hardware is unable to perform a successful recovery, then the link will automatically revert to
the polling state, and initiate a full retraining sequence. This is a drastic event with an implicit reset
to the downstream device and all subordinate devices, and is logged by the MCH as a Link Down
error. If escalation of this event is enabled, software is notified of the link DL_DOWN condition.
Once software is involved, data will likely be lost, and processes will needed to be restarted, but
this is still preferred to having to take the system down, or go offline for an extended period of
time.
5.6 Hub Interface 1.5
The MCH interfaces with the ICH via a dedicated Hub Interface 1.5 supporting a peak bandwidth
of 266 MB/s using a x4 base clock of 66 MHz.
This 8-bit Hub Interface (HI) provides a parity protection scheme for the data signals. The MCH HI
can be configured to either perform or not perform error checking on incoming data, heading
towards the MCH. When enabled, the MCH will mark incoming data as “poisoned” before passing
it on to its destination when parity errors are detected on the HI. Additionally, the MCH HI logic
has the capability to prevent the propagation of outbound data that has been marked as “poisoned”
at one of the other MCH interfaces when parity errors were detected on incoming data. See
Section 5.11, “Exception Handling” on page 5-245 for a complete discussion of the MCH error
handling capabilities.
5.7 MCH Clocking
Figure 5-12 details the operational frequency range for all MCH interfaces, and specifies all
supported relative interface frequencies. Operation of the MCH outside the frequency domains
stipulated here may result in system instability and failure.
External clock synthesizers and/or distribution buffers are responsible for generating the
differential host clock, PCI Express reference clock, HI clock, SMBus clock, and the JTAG clock
(when utilized). All these clocks are phase-independent, and no mode is provided within the MCH
to recover the added latency incurred from crossing the resultant asynchronous boundary within
Table 5-10. MCH Clocking Interfaces
Interface Clock Type Mnemonic Fmin Fmax Comments
System Bus
(host)
Differential HCLKIN 100 MHz 200 MHz
Input. Address at 2x,
Data at 4x
DDR (mem) Differential CMDCLK 100 MHz 200 MHz Output, geared to System Bus.
Hub Interface
(ICH)
Single-ended HICLK 50 MHz 66 MHz
Input. Asynchronous to
System Bus
PCI Express Differential EXP_CLK 100 MHz 100 MHz
Input. SSC tolerant, transmit at
25x, asynchronous to System
Bus
JTAG Single-ended TCLK 10 kHz 16.7 MHz
Input. TAP clock,
asynchronous to System Bus
SMBus Single-ended SMBSCL 10 kHz 100 kHz
I/O. Asynchronous to System
Bus
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