Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 231
Functional Description
than six independent PCI Express* ports of any width simultaneously, nor does it imply that the
remaining three lanes of a potential x4 port are useful once the associated link has been established
for x1operation.
The MCH supports PCI Express lane reversal at all native widths, and reversed x4 training on any
x8 port.
5.5.1 PCI Express Training
To establish a connection between PCI Express endpoints, they both participate in a sequence of
steps known as training. This sequence will establish the operational width of the link as well as
adjust skews of the various lanes within a link so that the data sample points can correctly take a
data sample off of the link. In the case of a x8 port, the x4 link pairs will first attempt to train
independently, and will collapse to a single link at the x8 width upon detection of a single device
returning link ID information upstream. Once the number of links has been established, they will
negotiate to train at the highest common width, and will step down in its supported link widths in
order to succeed in training. The ultimate result may be that the link trains as a x1 link. Although
the bandwidth of this link size is substantially lower than a x8 link or even a x4 link, it will allow
communication between the two devices. Software will then be able to interrogate the device at the
other end of the link to determine why it failed to train at a higher width (something that would not
be possible without support for the x1 link width). It should be noted that width negotiation is only
done during training or retraining, but not recovery.
5.5.2 PCI Express Retry
The PCI Express interface incorporates a link level retry mechanism. The hardware detects when a
transmission packet is corrupted and performs a retry of that particular packet and all following
packets. Although this will cause a temporary interruption in the delivery of packets, it does so in
order to maintain the link integrity.
5.5.3 PCI Express Link Recovery
When enough errors occur, the hardware may determine that the quality of the connection is in
question, and the end points can enter what amounts to a quick training sequence known as
recovery. The width of the connection will not be renegotiated, but the adjustment of skew between
lanes of the link may occur. This occurs without any software intervention, but the software may be
notified.
5.5.4 PCI Express Data Protection
The PCI Express high-speed serial interface makes use of traditional CRC protection. The data
packets will utilize a 32-bit CRC protection scheme, specifically the same CRC-32 used by
Ethernet – 0x04C11DB7. The smaller link packets will utilize a 16-bit CRC scheme. Since packets
utilize 8B/10B encoding, and not all encodings are used; this provides further data protection, as
illegal codes can be detected. Also, if errors are detected on the reception of data packets due to
various transients, these data packets can be retransmitted. Hardware logic will support this
link-level retry without software intervention.
