• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • QGE7520MC-SL8EE PDF文件及第230页内容在线浏览

QGE7520MC-SL8EE

QGE7520MC-SL8EE首页预览图
型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
  • QGE7520MC-SL8EE PDF在线浏览
功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝QGE7520MC-SL8EE
PDF页面索引
[1] 页[2] 页[3] 页[4] 页[5] 页[6] 页[7] 页[8] 页[9] 页[10] 页[11] 页[12] 页[13] 页[14] 页[15] 页[16] 页[17] 页[18] 页[19] 页[20] 页[21] 页[22] 页[23] 页[24] 页[25] 页[26] 页[27] 页[28] 页[29] 页[30] 页[31] 页[32] 页[33] 页[34] 页[35] 页[36] 页[37] 页[38] 页[39] 页[40] 页[41] 页[42] 页[43] 页[44] 页[45] 页[46] 页[47] 页[48] 页[49] 页[50] 页[51] 页[52] 页[53] 页[54] 页[55] 页[56] 页[57] 页[58] 页[59] 页[60] 页[61] 页[62] 页[63] 页[64] 页[65] 页[66] 页[67] 页[68] 页[69] 页[70] 页[71] 页[72] 页[73] 页[74] 页[75] 页[76] 页[77] 页[78] 页[79] 页[80] 页[81] 页[82] 页[83] 页[84] 页[85] 页[86] 页[87] 页[88] 页[89] 页[90] 页[91] 页[92] 页[93] 页[94] 页[95] 页[96] 页[97] 页[98] 页[99] 页[100] 页[101] 页[102] 页[103] 页[104] 页[105] 页[106] 页[107] 页[108] 页[109] 页[110] 页[111] 页[112] 页[113] 页[114] 页[115] 页[116] 页[117] 页[118] 页[119] 页[120] 页[121] 页[122] 页[123] 页[124] 页[125] 页[126] 页[127] 页[128] 页[129] 页[130] 页[131] 页[132] 页[133] 页[134] 页[135] 页[136] 页[137] 页[138] 页[139] 页[140] 页[141] 页[142] 页[143] 页[144] 页[145] 页[146] 页[147] 页[148] 页[149] 页[150] 页[151] 页[152] 页[153] 页[154] 页[155] 页[156] 页[157] 页[158] 页[159] 页[160] 页[161] 页[162] 页[163] 页[164] 页[165] 页[166] 页[167] 页[168] 页[169] 页[170] 页[171] 页[172] 页[173] 页[174] 页[175] 页[176] 页[177] 页[178] 页[179] 页[180] 页[181] 页[182] 页[183] 页[184] 页[185] 页[186] 页[187] 页[188] 页[189] 页[190] 页[191] 页[192] 页[193] 页[194] 页[195] 页[196] 页[197] 页[198] 页[199] 页[200] 页[201] 页[202] 页[203] 页[204] 页[205] 页[206] 页[207] 页[208] 页[209] 页[210] 页[211] 页[212] 页[213] 页[214] 页[215] 页[216] 页[217] 页[218] 页[219] 页[220] 页[221] 页[222] 页[223] 页[224] 页[225] 页[226] 页[227] 页[228] 页[229] 页[230] 页[231] 页[232] 页[233] 页[234] 页[235] 页[236] 页[237] 页[238] 页[239] 页[240] 页[241] 页[242] 页[243] 页[244] 页[245] 页[246] 页[247] 页[248] 页[249] 页[250] 页[251] 页[252] 页[253] 页[254] 页[255] 页[256] 页[257] 页[258] 页[259] 页[260] 页[261] 页[262] 页[263] 页[264] 页[265] 页[266] 页[267] 页[268] 页[269] 页[270] 页[271] 页[272] 页[273] 页[274] 页[275] 页[276] 页[277] 页[278] 页[279] 页[280] 页[281] 页[282] 页
120%
230 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
The idle_current and active_current are derived from DRAM device data-sheet values. Active
current is a composite of activate current and read command current, normalized for the weighting
factor used for activates. (i.e: Calculated value of datasheet read plus activate current, divided by
weight total to get a generic current value per active clock. The hardware weighting algorithm will
convert the generic active clock value back to the data sheet values on the fly. For a 3:2 ratio, the
normalized active current is 1/5 of the sum of activate current and read command current.)
Clocks per period is the number of DDR clocks in the global monitoring window (GDSW). The
GDSW is programmable in 4ms increments, with a range from 0 (disabled) up to 1.02 seconds.
Assuming the minimum 4ms GDSW, that would be 667K clocks per window for DDR333, and
533K for DDR266. The trade-off for GDSW size has two dimensions. Under normal operation the
GDSW period is non-managed, so its duration limits how long DRAM is run “too hot” before
thermal management commences, which would lead to a desire to keep GDSW on the smaller end
of the scale. But thermal effects have a fair amount of “inertia” because it takes time for a DRAM
package to change temperature, which leads to a desire to operate in fairly large time increments so
that thermal management is effective. The thermal management time (TT) field provides some
capability to play both ends against the middle, because the duration of thermal management is a
6-bit multiple of the GDSW. So it is possible to monitor GDSW at 16 ms granularity, and still use
thermal management for an entire second once the threshold has been crossed.
Once thermal management has been invoked, MCH hardware will enforce that no DIMM receives
more activity than that allowed by the value programmed into the “Thermal Management Activity
Maximum” (TAM) field in any given “Thermal Management Monitor Window” (TMW). The
threshold is again tracked per DIMM, so the total amount of memory activity may exceed the TAM
value, but once any DIMM exceeds TAM, no traffic will be sent to any DIMM until the current
TMW expires.
Putting all of that together, a sample GAT calculation for single-rank, x4, 512 Mb DDR333,
assuming a 16 ms GDSW, an inlet temperature of 45°C, and a theta-CA of 4.0, would yield the
following:
Threshold(16ms) = ((85 – 45)/(4.0 • 2.5)) – 1.890) • (2666,667) / 2.185 = 2575134 = 04E hex
A little more math: assuming that each cache line access took one activate and one read (in
dual-channel mode) each cache line then costs 5 off the threshold), and translates this threshold
value into an available bandwidth of around 2 GB/sec. Thermal Management would be rare under
these circumstances as only a very well behaved traffic pattern could pull that kind of bandwidth
out of a single DIMM pair.
5.5 PCI Express Interface
The MCH utilizes the PCI Express high-speed serial interface to allow for superior I/O bandwidth.
The MCH is compatible with the PCI Express Interface Specification, Rev 1.0a. A PCI Express
port is defined as a collection of lanes. Each lane consists of two striped differential pairs in each
direction (transmit and receive). Thus, a x8 port would contain eight transmit signal pairs and eight
receive signal pairs.
The raw bit-rate on the data pins of 2.5 Gbit/s, results in a real bandwidth per pair of 250 MB/s
given the 8/10 encoding used to transmit data across this interface. The result is a maximum
theoretical realized bandwidth on a x8 PCI Express port of 2 GB/s in each direction or an aggregate
of 4 GB/s.
The MCH provides three configurable x8 PCI Express* ports. Each of these x8 PCI Express* ports
may alternatively be configured as two independent x4 PCI Express* ports. An interface routed for
x8 operation may train with a link width of either a x8, x4 or x1. A x4 routed interface may train as
either x4 or x1. Note that this does not in any way imply a capability for the MCH to support more
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价