228 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
5.4.6 Thermal Management
The MCH provides a DDR thermal management method that selectively reduces accesses to
system memory when the access rate crosses the predetermined programmable threshold. In effect,
this mechanism enforces a “traffic limit” to any given DIMM slot; thereby providing a
hardware-enforced ceiling on power dissipation. While available, DDR2 is not expected to require
activation of the thermal management mechanism under any environmental conditions, as
dissipation is significantly lower at 1.8V than at 2.5V.
5.4.6.1 Thermal Management Algorithmic Description
The goal of thermal management is to keep DRAM devices below their maximum specified case
temperatures. To this end, the MCH algorithm is fairly straightforward. The amount of activity per
DIMM is tracked per fixed window of time, and compared against a programmed threshold value
set by the most restrictive DIMM. If any DIMM goes over the budget, the thermal management
mechanism engages, limiting traffic to the memory array at large for a fixed period of time to avoid
a thermal spike. Once the thermal management period has expired, the mechanism is rearmed to
look for further threshold crossings. Figure 5-10 provides an overview of how thermal
management is implemented in the MCH. A single threshold register is implemented to reduce
overhead, and to align with the “big hammer” nature of thermal management enforcement. Given
that the design cannot freely reorder traffic to avoid the “hot” DIMM, thermal management simply
limits all memory traffic while active.
Referring to Figure 5-10, the various sampling and monitoring windows and thresholds are
programmable settings in the DRAM thermal management control registers of the MCH (DTCL,
DTCU). Fields in these registers define the “z, y, and n” parameters, as well as the activity count
thresholds, and are set by firmware prior to enabling the thermal management feature.
Table 5-8. DDR Channel A Clock to DIMM assignment
Clock Signal Associated DIMM
DDRA_CMDCLK0 DIMM1 (closest to MCH)
DDRA_CMDCLK3 DIMM2
DDRA_CMDCLK2 DIMM3
DDRA_CMDCLK1 DIMM4 (farthest from MCH)
Table 5-9. DDR Channel B Clock to DIMM assignment
Clock Signal Associated DIMM
DDRB_CMDCLK3 DIMM1 (closest to MCH)
DDRB_CMDCLK1 DIMM2
DDRB_CMDCLK2 DIMM3
DDRB_CMDCLK0 DIMM4 (farthest from MCH)
