Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 227
Functional Description
5.4.4 Quad Word Ordering
The ordering of quad words to memory is dependent upon the mode of memory. The figures below
itemize the ordering.
5.4.5 DDR Clock Voltage Crossing (VOX) Calibration
The MCH uses one of the 4 clock pairs on each DDR channel to properly calibrate the voltage
crossing (VOX). The clocks used to determine VOX crossing are as follows:
DDRA_CMDCLK1/1# for channel A and DDRB_CMDCLK0/0# for channel B. The MCH
requires that these clocks be enabled to perform VOX calibration.
Figure 5-8 and Figure 5-9 enumerate the clock to DIMM assignments for channel A and B
respectively for a 4 DIMM per channel implementation. For a three or two DIMM per channel, use
the same assignments, but leave the DIMMs closest to the MCH as no connect.
Figure 5-6. Dual Channel Memory Read
Figure 5-7. Single Channel Memory Read
Figure 5-8. Dual Channel Memory Read, Mirrored Mode
Figure 5-9. Single Channel Memory Read, MIrrored Mode
Q0Ch A
Ch B
Q4
Q3
Q1
Q2
Q5
Q7Q6
Ch x Q0 Q4Q3Q1 Q2 Q5 Q7Q6
Ch A
Ch B
Ch A
Ch B
Q0 Q4
Q3
Q1
Q2
Q5
Q7Q6
DIMM0 DIMM2
(Read01 & A15=0) OR (Read01 & A15=1 & Retry)
Q0 Q4
Q3
Q1
Q2
Q5
Q7Q6
DIMM2 DIMM0
(Read01 & A15=1) OR (Read01 & A15=0 & Retry)
Q0 Q4
Q3
Q1
Q2
Q5
Q7Q6
DIMM2 DIMM0
(Read10 & A15=0) OR (Read10 & A15=1 & Retry)
Q0 Q4
Q3
Q1
Q2
Q5
Q7Q6
DIMM0 DIMM2
(Read10 & A15=1) OR (Read10 & A15=0 & Retry)
Ch x Q0 Q4 Q2 Q6Q3Q1 Q5 Q7
DIMM2 DIMM0