224 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
256Mb
DDR/ DDR2
8Meg, x8 512MB 13 x 10 x 2 Row 28 ‘0’ 9 8 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 8 dev 16KB Col AP 28 14 13 12 11 10 7 6 5 ‘0’
256Mb
DDR/ DDR2
16Meg, x4 1024MB 13 x 11 x 2 Row 29 ‘0’ 9 8 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 16 dev 32KB Col 28 AP 29 14 13 12 11 10 7 6 5 ‘0’
512Mb
DDR
16Meg, x8 1024MB 13 x 11 x 2 Row 29 ‘0’ 9 8 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 8 dev 32KB Col 28 AP 29 14 13 12 11 10 7 6 5 ‘0’
512Mb
DDR
32Meg, x4 2048MB 13 x 12 x 2 Row 30 ‘0’ 9 8 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 16 dev 64KB Col 30 28 AP 29 14 13 12 11 10 7 6 5 ‘0’
512Mb
DDR2
16Meg, x8 1024MB 14 x 10 x 2 Row 29 ‘0’ 9 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 8 dev 16KB Col AP 29 14 13 12 11 10 7 6 5 ‘0’
512Mb
DDR2
32Meg, x4 2048MB 14 x 11 x 2 Row 30 ‘0’ 9 8 30 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 16 dev 32KB Col 28 AP 29 14 13 12 11 10 7 6 5 ‘0’
1Gb
DDR
32Meg, x8 2048MB 14 x 11 x 2 Row 30 ‘0’ 9 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 8 dev 32KB Col 30 AP 29 14 13 12 11 10 7 6 5 ‘0’
1Gb
DDR
64Meg, x4 4096MB 14 x 12 x 2 Row 31 ‘0’ 9 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 16 dev 64KB Col 30 31 AP 29 14 13 12 11 10 7 6 5 ‘0’
1Gb
DDR2
16Meg, x8 2048MB 14 x 10 x 3 Row 30 30 9 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15
8 bks, 8 dev 16KB Col AP 29 14 13 12 11 10 7 6 5 ‘0’
1Gb
DDR2
32Meg, x4 4096MB 14 x 11 x 3 Row 31 30 9 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15
8 bks, 16 dev 32KB Col 31 AP 29 14 13 12 11 10 7 6 5 ‘0’
Table 5-5. Dual Channel Non-Symmetric Address Map (Sheet 2 of 2)
Tech
bank capacity,
width
Row Size
R/C/B ADDR BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
banks, num of
devices / DIMM
Page
Size