Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 223
Functional Description
When mirroring is enabled via MCH configuration, the memory subsystem maintains two copies
of all data as described above, and will retrieve requested data from either primary or mirror based
on the state of system address bit 15 (SA[15]). Software may toggle which SA[15] polarity selects
primary vs. mirror via a configuration register bit setting. SA[15] was chosen because it is the
lowest system address bit that is always used to select the memory row address across all DRAM
densities and technologies supported by the MCH. The toggling of the primary read location based
on an address bit will distribute request traffic across the primary and mirror DIMMs, thereby
distributing the thermal image of the workload across all populated DIMM slots, and reducing the
chances of thermal-based memory traffic throttling.
In the “Mirrored” operating state, the occurrence of correctable and uncorrectable ECC errors are
tracked and logged normally by the MCH, and escalated to system interrupt events as specified by
the configuration register settings associated with errors on the memory subsystem. Counters
implementing the “leaky bucket” function just described for on-line DIMM sparing track the
aggregate count of single-bit and multiple-bit errors on a per DIMM basis.
5.4.3 Memory Address Translation Tables
The following tables define the address bit translation from the system address to the DRAM
row/column/bank address. Note that the count of DRAM devices per DIMM listed in the following
tables excludes the devices utilized for ECC information, thus the actual DRAM counts in MCH
platforms are expected to be 9 devices per rank of x8 technology, and 18 devices per rank of x4
technology.
Figure 5-5. Eight DIMM Memory Mirror Configuration
MCH
D
I
M
M
A
2
D
I
M
M
B
2
Channel A
Channel B
Memory Subsystem
MirrorPrimary
D
I
M
M
B
3
D
I
M
M
A
1
D
I
M
M
B
1
D
I
M
M
B
4
D
I
M
M
A
4
Primary
Mirror
D
I
M
M
A
3
Table 5-5. Dual Channel Non-Symmetric Address Map (Sheet 1 of 2)
Tech
bank capacity,
width
Row Size
R/C/B ADDR BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
banks, num of
devices / DIMM
Page
Size
128Mb
DDR
4Meg, x8 256MB 12 x 10 x 2 Row 27 “0-” 9 8 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 8 dev 16KB Col AP 27 14 13 12 11 10 7 6 5 ‘0’
128Mb
DDR
8Meg, x4 512MB 12 x 11 x 2 Row 28 ‘0’ 9 8 26 25 24 23 22 21 20 19 18 17 16 15
4 bks, 16 dev 32KB Col 28 AP 27 14 13 12 11 10 7 6 5 ‘0’