222 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
Hardware in the MCH tracks which DIMM slots are primaries, and which are mirrors, such that
data may be internally realigned to correctly reassemble cache lines regardless of which copy is
retrieved. There are four distinct cases for retrieval of the “even” and “odd” chunks of a cache-line
of data:
• Interleaved dual-channel read to the primary DIMM with “even” data on channel A
• Interleaved dual-channel read to the mirror DIMM with “even” data on channel B
• Non-interleaved single-channel read pair to channel A with “even” data on the primary DIMM
• Non-interleaved single-channel read pair to channel B with “even” data on the mirror DIMM
Figure 5-3. Four DIMM Memory Mirror Configuration
D
I
M
M
A
2
D
I
M
M
A
3
D
I
M
M
B
2
D
I
M
M
B
3
Channel A
Channel
B
Memory Subsystem
Mirror Primary
Not
Populated
D
I
M
M
A
4
D
I
M
M
A
1
D
I
M
M
B
1
MCH
D
I
M
M
B
4
Figure 5-4. Six DIMM Memory Mirror Configuration (DDR2 only)
D
I
M
M
A
2
D
I
M
M
B
2
Channel A
Channel
B
Memory Subsystem
Mirror Primary
Not
Populated
D
I
M
M
A
3
D
I
M
M
B
3
D
I
M
M
A
1
D
I
M
M
B
1
Primary /
Mirror
MCH
D
I
M
M
B
4
D
I
M
M
A
4
