Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 221
Functional Description
This methodology implies that the first non-zero comparison will occur only after the first time
period has expired. Thus, an infinite time unit (bucket set to “never leak”) cannot generate a
threshold event regardless of how many errors have been counted.
5.4.2.6.2 Error Reporting
At the expiration of a time period, all counters, SEC and DED, are halved and compared against
their respective SEC and DED threshold registers. When an error counter exceeds its threshold, a
per DIMM flag bit is set in the DIMM_THR_EX register. This one register can be read to
determine if any DIMMs had an unexpected number of errors. Once software clears a flag bit in the
DIMM_THR_EX register, the threshold detect hardware is not rearmed for that DIMM until such
time that the error count decays to a value that matches or is less than the threshold value.
5.4.2.6.3 Sparing Implications
After a sparing operation has been performed, the spare DIMM will inherit the same SEC and DED
counters utilized by the failing DIMM. In order to avoid an immediate threshold exceeded error on
the new DIMM due to the error residue remaining in the counter from the failing DIMM, it is
necessary to clear the counter by adjusting the time period via the SPARECTL register to the
smallest non-zero value (1uS) and running for at least 10 time periods. The time period can then be
adjusted back to its desired value. The side affect of this is that the error accumulations for all other
DIMMs will essentially be cleared out as well, since they all use the same time period mechanism.
5.4.2.7 Memory Mirroring
The memory mirroring feature is fundamentally a way for hardware to maintain two copies of all
data in the memory subsystem, such that a hardware failure or uncorrectable error is no longer fatal
to the system. When an uncorrectable error is encountered during normal operation, hardware
simply retrieves the “mirror” copy of the corrupted data, and no system failure will occur unless
both primary and mirror copies of the same data are corrupt simultaneously (statistically very
unlikely).
Mirroring is supported on dual-channel DIMM populations symmetric both across channels and
within each channel. As a result, there are three supported configurations for memory mirroring:
• Four DIMM population of completely identical devices (two per channel). Referring to
Figure 5-3, DIMMs labeled A3, A4, B3 and B4 must be identical.
• Six DIMM population with identical devices in slot pairs 1/2 and 3 on each channel. Referring
to Figure 5-4, DIMMs labeled A2, A3, B2 and B3 must be single rank and identical and those
labeled A4 and B4 must be dual ranked and identical (but not necessarily identical to those in
the other group). This configuration is only valid with DDR2 memory.
• Eight DIMM population with identical devices in slot pairs 0/1 and 2/3 on each channel.
Referring to Figure 5-5, DIMMs labeled A1, A2, B1 and B2 must be identical and those
labeled A3, A4, B3 and B4 must be identical (but not necessarily to those in the other group).
These symmetry requirements are a side effect of the hardware mechanism for maintaining two
copies of all main memory data while ensuring that each channel has a full copy of all data in
preparation for fail-down to single-channel operation. Every write to memory is issued twice, once
to the “primary” location, and again to the “mirror” location, and the data interleaved across the
channel pair are swapped for the second write (A1 is a copy of B2, B1 is a copy of A2, etc.). The
resulting memory image has two full copies of all data, and a complete copy available on each
channel.
