Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 215
Functional Description
When the MCH drives data, each 16-bit segment is analyzed. The corresponding DBI# signal
asserts depending on the number of active data lines and the data path through the MCH.
• When data is driven by the MCH from memory to the FSB, the corresponding DBI# signal
asserts and data inverts if eight or more of the sixteen signals would normally be driven low.
Otherwise, the group is not inverted.
• For all other data driven by the MCH to the FSB, the corresponding DBI# signal asserts and
data inverts if more than eight of the sixteen signals would normally be driven low.
Otherwise, the group is not inverted.
This behavior ensures that the MCH drives low no more than eight data bits within a sixteen bit
group at any given time.
When the processor drives data, the MCH monitors DBI[3:0]# to determine if the corresponding
data segment requires inversion.
5.3.4 Front Side Bus Parity
Address/request, response, and data bus signals are protected by parity. The address/request and
data busses can be configured to perform no error checking.
The FSB data parity scheme is not straightforward parity, so a description is warranted. Note that
the data in a given clock cycle is quad-pumped while the parity that corresponds to this same data
is common-clocked driven in the clock following the presentation of the data. The four sub phases
correspond to the data and data inversion bits that will be driven out during a single clock cycle.
The corresponding parity bits are calculated by XORing the four table components. For example;
DP3# which will be driven out in the clock following the data is an XOR of DP3a, DP3b, DP3c,
and DP3d. As the Table 5-2 shows these four parity components are on different rows of the table.
Ultimately an approximate 32 bytes of data is protected by four parity bits. This particular rotating
parity scheme is able to detect stuck at faults more easily.
Table 5-1. DBI Signals to Data Bit Mapping
DBI[3:0]# Data Bits
DBI0# HD[15:0]
DBI1# HD[31:16]
DBI2# HD[47:32]
DBI3# HD[63:48]
Table 5-2. FSB Parity Matrix
Data Signals
Subphase
1 2 3 4
D[15:0]#, DBI0# DP3a DP2b DP1c DP0d
D[31:16]#, DBI1# DP0a DP3b DP2c DP1d
D[47:32]#, DBI2# DP1a DP0b DP3c DP2d
D[63:48]#, DBI3# DP2a DP1b DP0c DP3d