214 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Functional Description
5.3 Front Side Bus (FSB)
The MCH supports either single or dual processor population. System bus implementation of
arbitration and transaction identification allows for processors to operate in either single or
dual-threaded modes (Hyper-Threading technology) for a maximum of four logical processors.
The MCH supports a base system bus frequency of 200 MHz. The address and request interface is
double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz.
This provides a matched system bus address and data bandwidth of 6.4 GB/s.
5.3.1 In-Order Queue (IOQ)
The MCH has a 12 deep IOQ. This means that it does not need to limit the number of simultaneous
outstanding transactions by asserting BNR#.
5.3.2 System Bus Interrupts
Intel Xeon processors support FSB interrupt delivery. They do not support the APIC serial bus
interrupt delivery mechanism. Interrupt related messages are encoded on the FSB as “Interrupt
Message Transactions”. In the MCH, platform FSB interrupts may originate from one of the
processors on the FSB (IPIs – inter-processor interrupts), or from a downstream device on either
the Hub Interface (HI) or one of the PCI Express ports. In the latter case the MCH drives the
“Interrupt Message Transaction” onto the FSB.
In the IOxAPIC environment an interrupt is generated from the IOxAPIC to a processor in the form
of an upstream Memory Write. In the MCH environment, the ICH and PXH contain IOxAPICs,
and their interrupts are generated as upstream HI/PCI Express Memory Writes. Furthermore, PCI
2.3 defines MSIs (Message Signaled Interrupts) that are also in the form of Memory Writes. A PCI
2.3 device may generate an interrupt as an MSI cycle on its PCI bus instead of asserting a hardware
signal to the IOxAPIC. The MSI may be directed to the IOxAPIC, which in turn generates an
interrupt as an upstream HI/PCI Express Memory Write. Alternatively the MSI may be directed
directly to the FSB. The target of an MSI is dependent on the address of the interrupt Memory
Write. The MCH forwards inbound HI/PCI Express Memory Writes to address 0FEEx_xxxxh to
the FSB as “Interrupt Message Transactions”.
The MCH supports redirecting Lowest Priority delivery mode interrupts to the processor that is
executing the lowest priority task thread. The MCH redirects interrupts based on the task priority
status of each processor thread. The task priority of each processor thread is periodically
downloaded to the MCH via the xTPR (Task Priority register) Special Transaction. The MCH
redirects HI/PCI Express and PCI originated interrupts as well as IPIs.
The MCH also broadcasts EOI cycles generated by a processor downstream to the HI/PCI Express
interfaces.
5.3.3 System Bus Dynamic Inversion
The MCH supports Dynamic Bus Inversion (DBI) both when driving and when receiving data
from the system bus. DBI limits the number of data signals that are driven to a low voltage on each
quad pumped data phase. This decreases the power consumption of the MCH. DBI[3:0]# indicate
if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase. See
Table 5-1 for DBI to data bit mapping.
