Intel
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E7520 Memory Controller Hub (MCH) Datasheet 213
5 Functional Description
This chapter provides a functional description of the MCH architecture. Coverage includes the
MCH interface units (system bus, system memory, PCI Express, Hub Interface (HI), SMBus,
power management, MCH clocking, MCH system reset and power sequencing) as well as RASUM
(Reliability, Availability, Serviceability, Usability, and Manageability) features.
5.1 Internal Feature Set
5.1.1 Coherent Memory Write Buffer
The MCH integrates a coherent write buffer sized for 16, 64-byte cache lines (a total of 1 KB of
storage). This feature enables the MCH to optimize memory read latency, allowing reads to pass
less critical writes en route to the main memory store. The write buffer includes a CAM structure to
enforce ordering among conflicting accesses to the same cache line, as well as to provide for read
service from the write cache. In the latter case, the access to the main memory store never occurs,
which both improves latency and conserves bandwidth on the memory interface.
Note that the write buffer is capable of servicing processor read requests directly via a “hit” to the
internal location containing the data without initiation of any DDR subsystem accesses. Inbound
read requests which “hit” the write buffer result in a flush of the target data, followed by retrieval
via an external read request. The complexity of direct service for inbound read requests is not
warranted given the extremely modest hit rate expected for a 1-KB structure running server I/O
workloads.
5.1.2 Internal Data Protection
Due to the nature of having various data protection schemes on the different interfaces (ECC,
parity, and CRC) it is necessary to be able to convert between them when transferring data
internally. To accomplish this, protection of internal data is done with parity.
5.2 Integrated DMA Controller
The MCH includes an integrated four-channel direct memory access (DMA) controller to perform
background data transfers between locations in main memory, or from main memory to a
memory-mapped I/O destination. These transfers may be individually designated to be coherent
(snooped on the System Bus) or noncoherent (not snooped on the System Bus), providing
improvements in system performance and utilization when cache coherence is managed by
software rather than hardware.
Each of the four channels implements an independent set of configuration and status registers, and
is capable of fully independent operation. Each channel may operate in a single block transfer
mode, or a hardware traversed linked-list scatter/gather mode.
For additional information on the integrated DMA controller, contact your Intel Field
Representative.