210 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
System Address Map
4.3.1 SMM Addressing Ranges
The MCH provides three SMRAM options:
1. Below 1 MB option that supports compatible SMI handlers.
2. Above 1 MB option that allows new SMI handlers to execute with writeback cacheable
SMRAM.
3. Optional larger writeback cacheable T_SEG area from 128 KB to 1 MB in size. The above
1-MB solutions require changes to compatible SMRAM handler code to properly execute
above 1 MB.
Note that the first two options both map legal accesses to the same physical range of memory,
while the third defines an independent region of addresses.
4.3.1.1 SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and
may cause the system to hang:
The Compatible SMM space must not be set up as cacheable.
• Both D_OPEN and D_CLOSE must not be set to ‘1’ at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the Operating
System as available DRAM. This is a BIOS responsibility.
BIOS and SMM code must cooperate to properly configure the MCH in order to ensure reliable
operation of the SMM function.
4.3.1.2 SMM Space Definition
SMM space is defined by both its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of system bus addresses used by the processor to
access SMM space. DRAM SMM space is defined as the range of physical DRAM memory
locations containing SMM information.
SMM space can be accessed at one of three transaction address ranges: Compatible, High and
TSEG. The Compatible and TSEG SMM space not remapped; therefore the addressed and DRAM
SMM physical addresses are identical. The High SMM space is remapped; thus the addressed and
DRAM SMM locations are different. Note that the High DRAM space is the same as the
Compatible Transaction Address space.
Table 4-1 describes all three unique addressing combinations:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 4-1. Supported SMM Ranges
SMM Space Enabled Transaction Address Space DRAM Space
Compatible (C) A0000h to BFFFFh A0000h to BFFFFh
High (H) 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh
TSEG (T) (TOLM-TSEG_SZ) to TOLM (TOLM-TSEG_SZ) to TOLM
