Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 209
System Address Map
4.1.10.7 HI Subtractive Decode
All accesses that fall between the address programmed into the TOLM register and 4 GB are
subtractively decoded and forwarded to HI; that is, they will be mapped to HI if they do not
positively decode to a space that corresponds to another port/device. Any gaps in the map between
APIC, processor-specific, platform-specific, and compatibility PCI device memory regions fall
into this category. Note that the MCH does not support subtractive decode for transactions initiated
by the I/O subsystem; thus accesses which fall into this category received inbound will be specially
terminated, rather than forwarded to the HI.
4.2 I/O Address Space
The MCH does not support the existence of any other I/O devices on the system bus. The MCH
generates outbound transactions for all processor I/O accesses. The MCH contains two internal
registers in the processor I/O space, Configuration Address register (CONF_ADDR) and the
Configuration Data register (CONF_DATA). These locations are used to implement the
configuration space access mechanism and are described in the Device Configuration registers
section.
The processor allows 64 KB + 3 bytes to be addressed within the I/O space. The MCH propagates
the processor I/O address without any translation to the targeted destination bus. Note that the
upper three locations can be accessed only during I/O address wraparound when signal A16# is
asserted on the system bus. A16# is asserted on the system bus whenever a DWord I/O access is
made from address 0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software
attempts a two-byte I/O access from address 0FFFFh.
All I/O accesses (read or write) that do not target the MCH’s Configuration Address or Data
registers will receive a Defer Response on the system bus, and be forwarded to the appropriate
outbound port. The MCH never posts an I/O write.
The MCH never responds to inbound transactions to I/O or configuration space initiated on any
port. Inbound I/O or configuration transactions requiring completion are terminated with “master
abort” completion packets on the originating port interface. Outbound I/O or configuration write
transactions not requiring completion are dropped.
4.3 System Management Mode (SMM) Space
The MCH supports the use of main memory as System Management RAM (SMM RAM) enabling
the use of System Management Mode. The MCH supports three SMM options:
Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG).
• System Management RAM space provides an access-protected memory area that is available
for SMI handler code and data storage. This memory resource is normally hidden from the
Operating System so that the processor has immediate access to this memory space upon entry
to SMM (cannot be swapped out).
