Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 207
System Address Map
the 4GB boundary. The registers associated with prefetchable MMIO (PMBASE/PMLIMIT) have
been augmented by the PCI defined upper 32-bit base/limit register pair (PMBASU/PMLMTU),
although only the first nibble of each register is implemented in the MCH (physical addressing is
limited to 36 bits total).
The MBASE/MLIMIT pair must be programmed to lie between TOLM and 4GB. The
PMBASE/PMLIMIT and PMBASU/PMLMTU registers must be programmed to lie either
between TOLM and 4GB, or between the top of main memory and 64GB.
Because these registers define a PCI memory space, they are subject to the memory access enable
(MAEN) control bit in the standard PCI command register.
4.1.10.1 Device 2 Memory and Prefetchable Memory
Plug-and-play software configures the PCI Express A memory window in order to provide enough
memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose addresses fall
within these windows are decoded and forwarded to PCI Express A for completion. The address
ranges in this space are:
• M2 MBASE2 to MLIMIT2
• PM2 PMBASE2/PMBASU2 to PMLIMIT2/PMLMTU2
Note that neither region should overlap with any other fixed or relocatable area of memory.
4.1.10.2 Device 3 Memory and Prefetchable Memory
Plug-and-play software configures the PCI Express A1 memory window in order to provide
enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose
addresses fall within this window are decoded and forwarded to PCI Express A1 for completion.
The address ranges in this space are:
• M3 MBASE3 to MLIMIT3
• PM3 PMBASE3/PMBASU3 to PMLIMIT3/PMLMTU3
Note that neither region should overlap with any other fixed or relocatable area of memory.
Note: If PCI Express A is configured to operate in x8 mode, all functional space for PCI Express A1
disappears; effectively collapsing M3/PM3 to match the limit addresses of M2/PM2.