Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 205
System Address Map
4.1.6 PCI Express Enhanced Configuration Aperture
The address ranges in this space are:
• EXPREGION 0_E000_0000 to 0_EFFF_FFFF
PCI Express defines a memory-mapped aperture mechanism through which to access 4KB of PCI
configuration register space for each possible bus, device, and function number. This 4KB space
includes the compatible 256B of register offsets that are traditionally accessed via the legacy
CF8/CFC configuration aperture mechanism in I/O address space, making the enhanced
configuration mechanism a full superset of the legacy mechanism. The enhanced mechanism has
the advantage that full destination and type of access is specified in a single memory-mapped
uncacheable transaction on the FSB, which is both faster and more robust than the historical
I/O-mapped address and data register access pair.
The MCH places the enhanced configuration aperture at E000_0000h by default, as this is the first
contiguous 256MB location below the 4GB boundary available for such usage.
4.1.7 I/O APIC Memory Space
The address ranges in this space are:
Figure 4-3. 1 MB through 4 GB Memory Regions
High BIOS, optional
extended SMRAM
Hub Interface A
(always)
Local APIC Space
Hub Interface A
(always)
PCI Express
IO APIC Space
Hub Interface
IO APIC Space
1_0000_0000 (4GB)
FF00_0000
Top Of Low Memory (TOLM)
PCI Express Port
windows
Extended SMRAM
Space
ISA Hole
Main Memory Region
Optional
Main Memory Region
FEF0_0000
FEE0_0000
FEC8_6000
FEC8_0000
FEC0_0000
TOLM - TSEG
100C_0000
100A_0000
0100_0000 (16 MB)
00F0_0000 (15 MB)
0010_0000 (1 MB)
