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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 203
System Address Map
4.1.2 VGA and MDA Memory Spaces
VGAA 0_000A_0000 to 0_000A_FFFF
MDA 0_000B_0000 to 0_000B_7FFF
VGAB 0_000B_8000 to 0_000B_FFFF
These legacy address ranges are used on behalf of video cards to map a frame buffer or a
character-based video buffer into a dedicated location. By default, accesses to these ranges are
forwarded to HI. However, if the VGA_EN bit is set in one of the BCTRL configuration registers,
then transactions within the VGA and MDA spaces are sent to one of the PCI Express interfaces.
The VGA_EN bit may be set in one and only one of the BCTRL registers. Software must not set
more than one of the VGA_EN bits.
If the configuration bit EXSMRC.MDAP (see Section 3.5.29 on page 3-66) is set, then accesses
that fall within the MDA range will be sent to HI without regard for the VGAEN bits. Legacy
support requires the ability to have a second graphics controller (monochrome display adapter) in
the system. In a MCH system with PCI graphics installed, accesses in the standard VGA range may
be forwarded to any of the logical PCI Express ports (depending on configuration bits). Since the
monochrome adapter may be on the HI/PCI (or logical ISA) bus, the MCH must decode cycles in
the MDA range and forward them to HI. This capability is controlled via the MDAP configuration
bit. In addition to the memory range B0000h to B7FFFh, the MCH decodes I/O cycles at 3B4h,
3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to HI.
An optimization allows the system to reclaim the memory displaced by these regions. If SMM
memory space is enabled by SMRAM.G_SMRAME and either the SMRAM.D_OPEN bit (see
Section 3.5.29 on page 3-66 and Section 3.5.30 on page 3-67) is set or the system bus receives an
SMM-encoded request for code (not data), then the transaction is steered to system memory rather
than HI. Under these conditions, both the VGAEN bits and the MDAP bit are ignored.
4.1.3 PAM Memory Spaces
The address ranges in this space are:
PAMC0 0_000C_0000 to 0_000C_3FFF
PAMC4 0_000C_4000 to 0_000C_7FFF
PAMC8 0_000C_8000 to 0_000C_BFFF
PAMCC 0_000C_C000 to 0_000C_FFFF
PAMD0 0_000D_0000 to 0_000D_3FFF
PAMD4 0_000D_4000 to 0_000D_7FFF
PAMD8 0_000D_8000 to 0_000D_BFFF
PAMDC 0_000D_C000 to 0_000D_FFFF
PAME0 0_000E_0000 to 0_000E_3FFF
PAME4 0_000E_4000 to 0_000E_7FFF
PAME8 0_000E_8000 to 0_000E_BFFF
PAMEC 0_000E_C000 to 0_000E_FFFF
PAMF0 0_000F_0000 to 0_000F_FFFF
The 256-KB PAM region is divided into three parts:
ISA expansion region, a 128-KB area between 0_000C_0000h0_000D_FFFFh
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