200 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.14.15 DTCU – DRAM Power Management Control Upper Register
(D8:F0)
Address Offset: D4 – D7h
Access: RO, R/W
Size: 32 Bits
Default: 0000_0000h
DTCL and DTCU make up a conceptual 64-bit register.
Bit Field
Default &
Access
Description
31:30 00b
R/W
Thermal Management Lock (TLOCK). These bits secure the DRAM thermal
management control registers. The bits default to ‘0’. Once a ‘1’ is written to either
bit, the configuration register bits in DTC become read-only, and no later writes
can change the register until reset. See exception to this statement for ST below.
NOTE: This register is not sticky.
00 = Not locked. All of the bits in DTC can be written.
01 = START Mode bits not locked. All bits in DTC(U&L) except for the ST
(DTCL bit 0) is locked and cannot be written to (including bits 31:30 of this
register).
10 = All bits locked. DTC is fully locked and cannot be changed, including bits
31:30 of this register.
11 = Reserved
29 0b
R/W
Thermal Management Test Mode Enable (TME). This bit is used to shorten test
time.
0 = Normal operation
1 = Global DRAM Sampling Window, and the Global Activate Threshold are
scaled down by ~1000. GDSW becomes a specification of microseconds
rather than milliseconds and GAT is multiplied by 32 rather than 32k.
28:21 00h Reserved
20:13 00h
R/W
Global DRAM Sampling Window (GDSW). This 8b value is multiplied by 4 to
define the length of time in milliseconds (0-1020). If the weighted activity count
during this window exceeds the Global Activity Threshold defined below, then the
thermal management mechanism will be invoked to limit DRAM requests to a
lower bandwidth checked over smaller time windows across all DIMM slots.
12:0 000h
R/W
Global Activity Threshold (GAT). This 13b value is multiplied by 2
15
to arrive at
the weighted activity count that must occur on a DIMM slot within the Global
DRAM Sampling Window in order to cause the thermal management mechanism
to be invoked.