20 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Introduction
1.2 Reference Documentation
1.3 Intel
®
E7520 MCH System Architecture
The architecture of the MCH provides the performance and feature set required for dual
processor-based volume to performance servers, with configuration options facilitating
optimization of the platform for workloads characteristic of communication, presentation, storage,
performance computation, or database applications. To accomplish this, the MCH has numerous
RASUM (Reliability, Availability, Serviceability, Usability and Manageability) features on
multiple interfaces. Detailed descriptions of the interfaces and RASUM features are provided in
Chapter 5, “Functional Description”.
The MCH consists of the following components: Memory Controller Hub (MCH), ICH, and the
Intel
®
6700PXH 64-bit PCI Hub. Although a brief overview is provided here, detailed component
information can be found in each device's respective documentation.
1.3.1 64-bit Intel
®
Xeon™ Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions)
The MCH supports either single or dual population of the Xeon processors. The front side bus
supports a base system bus frequency of 200 MHz. The address and request interface is double
pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz. This
provides a matched system bus address and data bandwidths of 6.4 GB/s.
1.3.2 Memory Subsystem
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR266, DDR333 or DDR2-400 memory (single or dual rank).When both DDR
channels are populated and operating, they function in lock-step mode. There are numerous
RASUM features for the MCH memory interface:
Document
Document
Number / Sources
Double Data Rate (DDR) SDRAM Specification http://www.jedec.org/
Intel
®
6700PXH 64-bit PCI Hub Datasheet http://developer.intel.com/
Intel
®
82801ER I/O Controller Hub 5 R (ICH5R) Datasheet http://developer.intel.com/
Intel
®
6300 ESB I/O Controller Datasheet http://developer.intel.com/
Intel
®
Xeon™ Processor with 800 MHz System Bus Datasheet http://developer.intel.com/
PCI Local Bus Specification, Rev 2.3 http://www.pcisig.com/home
PCI-X Addendum to the PCI Local Bus Specification, Rev 1.0b http://www.pcisig.com/home
PCI Express Interface Specification, Rev 1.0a http://www.pcisig.com/home
System Management Bus (SMBus) Specification, Rev 2.0 http://www.smbus.org
PCI Bus Power Management Interface Specification, Rev 1.1 http://www.pcisig.com/home
Advanced Configuration and Power Interface Specification (ACPI) http://www.acpi.info
PCI Standard Hot-Plug Controller and Subsystem Specification, Rev. 1.0 http://www.pcisig.com/home
