Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 199
Register Descriptions
Bit Field
Default &
Access
Description
31:30 00b Reserved
29:28 10b
R/W
Transaction Weighting. These two bits select the weighting between activate
and read/write commands.
A read or write will increment the throttle counter by 2. The activate command will
increment the counter by the amount specified by this two-bit field. In a given
cycle, a read or write can occur along with an activate to a different DIMM. Two
different DIMM slot counters would be incremented for this cycle. Activate:
read/write ratio.
00 = 2:2 (Increment by 2 for an activate, increment by 2 for a read or write)
01 = 3:2 (Increment by 3 for an activate, increment by 2 for a read or write)
10 = 4:2 (Increment by 4 for an activate, increment by 2 for a read or write)
11 = 5:2 (Increment by 5 for an activate, increment by 2 for a read or write)
27:22 00h
R/W
Thermal Management Time (TT). This value provides a multiplier between 0 and
63, which specifies how long thermal management remains in effect as a number
of Global DRAM Sampling Windows.
For example, if GDSW is programmed to 1000_0000b and TT is set to 01_0000b,
then thermal management will be performed for ~8 seconds once invoked (128 •
4ms • 16).
21:15 00h
R/W
Thermal Management Monitoring Window (TMW). The value in this register is
shifted left by 4 to specify a window of 0-2047 host clocks with a 16 clock
granularity. While the thermal management mechanism is invoked, DRAM
activate, reads, and writes are monitored during this window. If the weighted
activity count during the window reaches the Thermal Management Activity
Maximum for any DIMM slot, then requests are blocked for the remainder of the
window for all DIMM slots.
14:3 000h
R/W
Thermal Management Activity Maximum (TAM). This value defines the
maximum weighted activity count, between 0-4095, which is permitted to occur on
a DIMM slot within one TMW.
2:1 00b
R/W
Thermal Management Mode (RM).
00 = Thermal management via counters and hardware throttle_on signal
mechanisms disabled.
01 = Reserved
10 = Counter mechanism controlled through GDSW and GAT is enabled. When
the threshold set in GDSW and GAT is reached, thermal management
start/stop cycles occur based on the setting in TT, TMW and TAM.
11 = Reserved
0 0b
R/W
Start Thermal Management (ST). Software writes to this bit to start and stop the
write to thermal management.
0 = Write thermal management stops and the counters associated with TMW
and TAM are reset.
1 = Write thermal management begins based on the settings in TMW and TAM;
and remains in effect until this bit is reset to ‘0’.
