198 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.14.14 DTCL – DRAM Power Management Control Lower Register
(D8:F0)
Address Offset: D0 – D3h
Access: RO, R/W
Size: 32 Bits
Default: 2000_0000h
DTCL and DTCU make up a conceptual 64-bit register. This thermal management mechanism is
used for activates, reads, and writes. The memory subsystem uses this register to apply on a per
DIMM basis. Once thermal management is invoked, no transactions are issued to the entire
memory subsystem.
30:29 00b Reserved
28:0 000_000h
R/W
Starting Scrub Address. This corresponds to address bits 34:6 of the scrub
address, which is always 64B line based.
Bit Field
Default &
Access
Description