Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 197
Register Descriptions
3.14.12 SCRUBLIM – Scrub Limit and Control Register (D8:F0)
Address Offset: C8 – CBh
Access: RO, R/W, R/WS
Size: 32 Bits
Default: 0000_0000h
This register is used to load the scrub engine with a particular limit address and other control
information, such as the initialization data pattern.
3.14.13 SCRBADD – Scrub Address (D8:F0)
Address Offset: CC – CFh
Access: RO, R/W
Size: 32 Bits
Default: 0000_0000h
This register is used to load the scrub engine with a particular starting address. The scrub will be
performed between this address and the address in the scrub limit register.
Bit Field
Default &
Access
Description
31 0b
R/WS
Scrublim Valid.
0 = The hardware will clear this bit back to ‘0’ as it loads these values, therefore
software should never expect to read ‘1’ on this bit.
1 = The contents of this register will take affect on the next scrub address
update.
30:29 00b Reserved
28 0b
R/W
Mask periodic scrubbing.
0 = Writes for the periodic scrubs are performed
1 = Writes for the periodic scrubs are not performed
27 0B
R/W
Mask demand scrubbing.This bit when changed takes affect immediately and
does not require the scrublim valid bit to be written to a 1.
0 = Writes for the demand scrubs are performed
1 = Writes for the demand scrubs are not performed
26:15 000h Reserved
14:0 000h
R/W
Limit Address. Defines address bits [34:20] to limit the top of the address range
used for scrubs. These address bits require the scrublim valid bit to be written to a
1 in order to take affect on the next scrub address update.
Bit Field
Default &
Access
Description
31 0b
R/W
Scrbadd Valid.
0 = The hardware will clear this bit back to ‘0’ as it loads the scrub address from
bits 27:0, therefore software should never expect to read ‘1’ on this bit.
1 = The value of the address in bits 27:0 will be loaded into the scrub unit on the
next scrub address update.
NOTE: The address is loaded at the counter rollover time, which isn’t externally
visible. Therefore it is possible that after this register is written, there will be one
more scrub using the internal counter address, instead of the address placed in
this register. There will never be more than one ‘extra’ scrub before the value of
this register is used.
