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QGE7520MC-SL8EE

型号：	QGE7520MC-SL8EE
PDF文件：
功能描述：	IntelÂ® E7520 Memory Controller Hub (MCH)
PDF文件大小：	2594.09 Kbytes
PDF页数：	共282页
制造商：	INTEL[Intel Corporation]
制造商LOGO：
制造商网址：	http://www.intel.com

QGE7520MC-SL8EE

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120%

194 Intel

E7520 Memory Controller Hub (MCH) Datasheet

3.14.4 PCISTS – PCI Status Register (D8:F0)

Address Offset: 06 – 07h

Access: RO

Size: 16 Bits

Default: 0080h

PCISTS is a 16-bit status register that reports the occurrence of error events on Device 8’s PCI

interface. Since MCH Device 8 does not physically reside on a real PCI bus, many of the bits are

not implemented.

3.14.5 RID – Revision Identification (D8:F0)

Address Offset: 08h

Access: RO

Size: 8 Bit

Default: 09h

This register contains the revision number of MCH Device 8.

Bit

Field

Default &

Access

Description

15 0b

Detected Parity Error (DPE). Not implemented for Device 8.

14 0b

Signaled System Error (SSE). Not implemented for Device 8.

13 0b

Received Master Abort Status (RMAS). Not implemented for Device 8.

12 0b

Received Target Abort Status (RTAS). Not implemented for Device 8.

11 0b

Signaled Target Abort Status (STAS). Not implemented for Device 8.

10:9 00b

DEVSEL Timing (DEVT). Device 8 does not physically connect to PCI_A. These bits

are set to 00 (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by

the MCH.

8 0b

Master Data Parity Error Detected (DPD). Not implemented for Device 8.

7 1b

Fast Back-to-Back (FB2B). Device 8 does not physically connect to PCI_A. This bit is

set to ‘1’ (indicating fast back-to-back capability) so that the optimum setting for PCI_A

is not limited by the MCH.

6:0 00h Reserved

Bit Field

Default &

Access

Description

7:0 09h

Revision Identification Number (RID). This value indicates the revision

identification number for MCH Device 8.

09h = C1 stepping.

0Ah = C2 stepping.

0Ch = C4 stepping.

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