190 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
22 – 23h MLIMIT Memory Limit Address Register R/W 0000h
24 – 25h PMBASE Prefetchable Memory Base Address
Reg.
R/W, RO FFF1h
26 – 27h PMLIMIT Prefetchable Memory Limit Address Reg. R/W, RO 0001h
28h PMBASU Prefetchable Mem Base Upper Addr.
Reg.
RO, R/W 0Fh
2Ch PMLMTU Prefetchable Memory Limit Upper
Address Register
RO, R/W 00h
34h CAPPTR Capabilities Pointer RO 50h
3Ch INTRLINE Interrupt Line Register R/W 00h
3Dh INTRPIN Interrupt Pin Register R/WO 01h
3Eh BCTRL Bridge Control Register RO, R/W 00h
44h VS_CMD0 Vendor-Specific Command Register 0 RO 00h
45h VS_CMD1 Vendor-Specific Command Register 1 RO, R/W,
R/WS
00h
46h VS_STS0 Vendor-Specific Status Register 0 RO 00h
47h VS_STS1 Vendor-Specific Status Register 1 RO, R/WC 00h
50h PMCAPID Power Management Capabilities
Structure
RO 01h
51h PMNPTR Power Management Next Capabilities
Pointer
RO 58h
52 – 53h PMCAPA Power Management Capabilities RO C822h
54 – 55h PMCSR Power Management Status and Control RO,R/W 0000h
56h PMCSRBSE Power Management Status and Control
Bridge Extensions
RO 00h
57h PMDATA Power Management Data RO 00h
58h MSICAPID MSI Capabilities Structure RO 05h
59h MSINPTR MSI Next Capabilities Pointer RO 64h
5A – 5Bh MSICAPA MSI Capabilities RO, R/W 0002h
5C – 5Fh MSIAR MSI Address Register for PCI Express* R/W FEE0_0000h
60h MSIDR MSI Data Register R/W 0000h
64h EXP_CAPID PCI Express Features Capabilities
Structure
RO 10h
65h EXP_NPTR PCI Express Next Capabilities Pointer RO 00h
66 – 67h EXP_CAPA PCI Express Features Capabilities RO, R/WO 0041h
68 – 6Bh EXP_DEVCAP PCI Express Device Capabilities RO 0002_8001h
6C – 6Dh EXP_DEVCTL PCI Express Device Control R/W. RO 0000h
6E – 6Fh EXP_DEVSTS PCI Express Device Status RO, R/WC 0000h
70 – 73h EXP_LNKCAP PCI Express Link Capabilities RO 0703_E441h
74 – 75h EXP_LNKCTL PCI Express Link Control RO, R/W,
WO
0000h
76 – 77h EXP_LNKSTS PCI Express Link Status RO 1001h
78 – 7Bh EXP_SLTCAP PCI Express Slot Capabilities RO, R/WO 0000_0000h
7C – 7Dh EXP_SLTCTL PCI Express Slot Control R/W 01C0h
7E – 7Fh EXP_SLTSTS PCI Express Slot Status RO, R/WC 0040h
80 – 83h EXP_RPCTL PCI Express Root Port Control R/W 0000_0000h
84 – 87h EXP_RPSTS PCI Express Root Port Status RO, R/WC 0000_0000h
Table 3-12. PCI Express Port C1 PCI Configuration Register Map (D7:F0) (Sheet 2 of 3)
Address
Offset
Mnemonic Register Name Access Default