186 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
Except for the registers listed below, all registers for Device 5 are exactly as for Device 3. See
Section 3.8 for the remaining register definitions.
3.11.1 DID – Device Identification (D5:F0)
Address Offset: 02 – 03h
Access: RO
Size: 16 Bits
Default: 3598h
3.12 PCI Express Port C Registers (D6:F0)
Device 6 is the PCI Express port C (in x8 mode) or port C0 (in x4 mode) virtual PCI-to-PCI bridge.
This port supports Hot-Swap functionality.
118 – 11Bh EXP_AERCACR PCI Express Advanced Error Capabilities
and Control
RO, R/W 0000_0000h
11C – 11Fh EXP_HDRLOG0 PCI Express Header Log DW0 RO 0000_0000h
120 – 123h EXP_HDRLOG1 PCI Express Header Log DW1 RO 0000_0000h
124 – 127h EXP_HDRLOG2 PCI Express Header Log DW2 RO 0000_0000h
128 – 12Bh EXP_HDRLOG3 PCI Express Header Log DW3 RO 0000_0000h
12C – 12Fh EXP_RPERRCMD PCI Express Root Port Error Command R/W 0000_0000h
130 – 133h EXP_RPERRMSTS PCI Express Root Port Error Message
Status
RO, R/WC 0000_0000h
134 – 137h EXP_ERRSID PCI Express Error Source ID RO 0000_0000h
140 – 143h EXP_UNITERR PCI Express Unit Error Status RO, R/WC 0000_0000h
144 – 147h EXP_MASKERR PCI Express Mask Error RO, R/W 0000_E000h
148 – 14Bh EXP_ERRDOCMD PCI Express Error Do Command
Register
RO, R/W 0000_0000h
14C – 14Fh EXP_UNCERRDMSK PCI Express Uncorrectable Error Detect
Mask
RO, R/W 0000_0000h
150 – 153h EXP_CORERRDMSK PCI Express Correctable Error Detect
Mask
R/W 0000_0000h
158 – 15Bh EXP_UNITERRDMSK PCI Express Unit Error Detect Mask R/W 0000_0000h
160 – 163h EXP_FERR PCI Express First Error R/WC 0000_0000h
164 – 167h EXP_NERR PCI Express Next Error R/WC 0000_0000h
168 – 16Bh EXP_ERR_CTL PCI Express Error Control R/W 0000_0000h
Table 3-10. PCI Express Port B1 PCI Configuration Register Map (D5:F0) (Sheet 3 of 3)
Address
Offset
Mnemonic Register Name Access Default
Bit Field
Default &
Access
Description
15:0 3598h
RO
Device Identification Number (DID). This is a 16 bit value assigned to MCH
Device 5, Function 0.