18 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Introduction
DP Dual Processor
Dual Address
Cycle (DAC)
As described in the PCI Local Bus Specification, Rev 2.3, Dual Address Cycles are used
by PCI devices that utilize 64-bit addressing for memory transactions.
DW
Double Word. A reference to 32 bits of data on a naturally aligned four-byte boundary
(i.e., the least significant two bits of the address are 00b).
ECC Error Correcting Code
Gb/s Gigabits per second (10
9
bits per second)
GB/s Gigabytes per second (10
9
bytes per second)
Host This term is used synonymously with “processor.”
Hub Interface (HI) Proprietary interface that connects the MCH to the ICH.
I/O
1. Input/Output.
2. When used as a qualifier to a transaction type, specifies that transaction targets
Intel® Architecture-specific I/O space. (e.g., I/O read)
ICH
Intel
®
I/O Controller Hub (ICH) component. This refers to the Intel
®
82801ER I/O
Controller Hub 5 R (ICH5R)or Intel
®
6300ESB ICH.
Implicit Writeback
A snoop initiated data transfer from the bus agent with the modified Cache Line to the
memory controller due to an access to that line.
Inbound
A transaction where the request destination is the processor-memory complex and is
sourced from I/O. The terms Inbound and Outbound refer to transactions as a whole and
never to Requests or Completions in isolation. For example, an Inbound Read generates
Downstream data, whereas an Inbound Write has Upstream data. The Completion to an
Inbound Read travels Downstream.
Initiator
The source of requests. For example, an agent sending a request packet on a PCI
Express interface is referred to as the Initiator for that Transaction. The Initiator may
receive a completion for the Request.
Layer
A level of abstraction commonly used in interface specifications as a tool to group
elements related to a basic function of the interface within a layer and to identify key
interactions between layers.
Legacy
Functional requirements handed down from previous chipsets or PC compatibility
requirements from the past.
Link A full duplex transmission path between any two PCI Express devices.
LSb Least Significant Bit
LSB Least Significant Byte
Master
A device or logical entity that is capable of initiating transactions. A Master is any
potential Initiator.
MB/s Megabytes per second (10
6
bytes per second)
MCH Memory Controller Hub
Mem Used as a qualifier for transactions that target memory space. (e.g., a Mem read to I/O)
MSb Most Significant Bit
MSB Most Significant Byte
MSI
Message Signaled Interrupt. MSIs allow a PCI device to request interrupt service via a
Memory Write transaction rather than a hardware signal.
Non-coherent
Transactions that may cause the processor's view of memory through the cache to be
different with that obtained through the I/O subsystem.
Outbound
A transaction where the request destination is I/O and is sourced from the
processor-memory complex. The terms Inbound and Outbound refer to transactions as
a whole and never to Requests or Completions in isolation. For example, an Outbound
Read generates Upstream data, whereas an Outbound Write has Downstream data.
The Completion to an Outbound Read travels Upstream.
Packet The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
Plesiochronous
Each end of a link uses an independent clock reference. Support of this operational
mode places restrictions on the absolute frequency difference, as specified by PCI
Express, which can be tolerated between the two independent clock references.
Term Description