Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 179
Register Descriptions
59h MSINPTR MSI Next Capabilities Pointer RO 64h
5A – 5Bh MSICAPA MSI Capabilities RO, R/W 0002h
5C – 5Fh MSIAR MSI Address Register for PCI Express R/W FEE0_0000h
60h MSIDR MSI Data Register R/W 0000h
64h EXP_CAPID PCI Express Features Capabilities
Structure
RO 10h
65h EXP_NPTR PCI Express Next Capabilities Pointer RO 00h
66 – 67h EXP_CAPA PCI Express Features Capabilities RO, R/WO 0041h
68 – 6Bh EXP_DEVCAP PCI Express Device Capabilities RO 0002_8001h
6C – 6Dh EXP_DEVCTL PCI Express Device Control R/W. RO 0000h
6E – 6Fh EXP_DEVSTS PCI Express Device Status RO, R/WC 0000h
70 – 73h EXP_LNKCAP PCI Express Link Capabilities RO 0303_E441h
74 – 75h EXP_LNKCTL PCI Express Link Control RO, R/W,
WO
0000h
76 – 77h EXP_LNKSTS PCI Express Link Status RO 1001h
78 – 7Bh EXP_SLTCAP PCI Express Slot Capabilities RO, R/WO 0000_0000h
7C – 7Dh EXP_SLTCTL PCI Express Slot Control R/W 03C0h
7E – 7Fh EXP_SLTSTS PCI Express Slot Status RO, R/WC 0040h
80 – 83h EXP_RPCTL PCI Express Root Port Control R/W 0000_0000h
84 – 87h EXP_RPSTS PCI Express Root Port Status RO, R/WC 0000_0000h
C4 – C7h EXP_PFCCA PCI Express Posted Flow Control Credits
Allocated
RO 000C_0030h
C8 – CBh EXP_NPFCCA PCI Express Non Posted Flow Control
Credits Allocated
RO 0008_0001h
100 – 103h EXP_ENHCAPST PCI Express Enhanced Capability
Structure
RO 0001_0001h
104 – 107h EXP_UNCERRSTS PCI Express Uncorrectable Error Status RO, R/WC 0000_0000h
108 – 10Bh EXP_UNCERRMSK PCI Express Uncorrectable Error Mask RO, R/W 0000_0000h
10C – 10Fh EXP_UNCERRSEV PCI Express Uncorrectable Error
Severity
RO, R/W 0006_0011h
110 – 113h EXP_CORERRSTS PCI Express Correctable Error Status R/WC 0000_0000h
114 – 117h EXP_CORERRMSK PCI Express Correctable Error Mask R/W 0000_0000h
118 – 11Bh EXP_AERCACR PCI Express Advanced Error Capabilities
and Control
RO, R/W 0000_0000h
11C – 11Fh EXP_HDRLOG0 PCI Express Header Log DW0 RO 0000_0000h
120 – 123h EXP_HDRLOG1 PCI Express Header Log DW1 RO 0000_0000h
124 – 127h EXP_HDRLOG2 PCI Express Header Log DW2 RO 0000_0000h
128 – 12Bh EXP_HDRLOG3 PCI Express Header Log DW3 RO 0000_0000h
12C – 12Fh EXP_RPERRCMD PCI Express Root Port Error Command R/W 0000_0000h
130 – 133h EXP_RPERRMSTS PCI Express Root Port Error Message
Status
RO, R/WC 0000_0000h
134 – 137h EXP_ERRSID PCI Express Error Source ID RO 0000_0000h
140 – 143h EXP_UNITERR PCI Express Unit Error Status RO, R/WC 0000_0000h
144 – 147h EXP_MASKERR PCI Express Mask Error RO, R/W 0000_E000h
Table 3-8. PCI Express Port A1 PCI Configuration Register Map (D3:F0) (Sheet 2 of 3)
Address
Offset
Mnemonic Register Name Access Default