176 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.77 EXP_FERR – PCI Express First Error Register (D2:F0)
Address Offset: 160 – 163h
Access: R/WC
Size: 32 Bits
Default: 0000_0000h
Captures the first error in each category type. These bits are sticky through reset. This register is
specific to the MCH.
Note: If multiple errors are reported in the same clock as the first error, all errors are latched.
Bit Field
Default &
Access
Description
31:9 00_0000h Reserved
8 0b
R/WC
Device Fatal Error Detected. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Internal Fatal Error Detected
7 0b
R/WC
Device Nonfatal Error Detected. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Device Nonfatal Error Detected
6 0b
R/WC
Device Correctable Error Detected. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Device Correctable Error Detected
5 0b
R/WC
Unit Specific Fatal Error Detected. This bit is for fatal errors not in the PCI
Express Interface Specification, Rev 1.0a as logged by the EXP_UNITERR
register. The EXP_MASKERR register only prevents reporting of the unit
errors, but does not prevent the logging of errors in this register. This bit is
sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Unit Fatal Error Detected
4 0b
R/WC
Unit Specific Non-fatal Error Detected. This bit is for non-fatal errors not in
the PCI Express Specification as logged by the EXP_UNITERR register. The
EXP_MASKERR register only prevents reporting of the unit errors, but does
not prevent the logging of errors in this register. This bit is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Unit Nonfatal Error Detected
3 0b
R/WC
Unit Specific Correctable Error Detected. This bit is for correctable errors
not in the PCI Express Specification as logged by the EXP_UNITERR register.
The EXP_MASKERR register only prevents reporting of the unit errors, but
does not prevent the logging of errors in this register. This bit is sticky through
reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Unit Correctable Error Detected
2 0b
R/WC
Fatal Error Message received. This bit is set when an ERR_FATAL message
is received. These received fatal error messages can be masked by the SERR
enable bit in the Bridge Control register, if the SERR enable bit is a ‘0’. This bit
is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Fatal Error Detected