Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 175
Register Descriptions
Bit Field
Default &
Access
Description
31:16 0000h Reserved
15 0b
R/W
Upstream Posted Queue Overflow Detect Mask. This bit is sticky through reset.
0 = Enable upstream posted queue overflow detection.
1 = Disable upstream posted queue overflow detection
14 0b
R/W
Upstream Non-Posted Queue Overflow Detect Mask. This bit is sticky through
reset.
0 = Enable upstream non-posted queue overflow detection.
1 = Disable upstream non-posted queue overflow detection
13 0b
R/W
Upstream Completion Queue Overflow Detect Mask. This bit is sticky through
reset.
0 = Enable completion queue overflow detection.
1 = Disable completion queue overflow detection
12 0b
R/W
LLE Protocol Error Detect Mask. This bit is sticky through reset.
0 = Enable LLE protocol error detection.
1 = Disable LLE protocol error detection
11 0b
R/W
Link Down Error Detect Mask. Mask detection of link transitions from DL_UP to
DL_DOWN. This bit is sticky through reset.
0 = Enable link down error detection.
1 = Disable link down error detection
10 0b
R/W
Downstream Data Queue Parity Error Detect Mask. This bit is sticky through
reset.
0 = Enable downstream data queue parity error detection.
1 = Disable downstream data queue parity error detection
9 0b
R/W
LUT Parity Error Detect Mask. This bit is sticky through reset.
0 = Enable LUT parity error detection.
1 = Disable LUT parity error detection
8 0b
R/W
LLRB Data Parity Error Detect Mask. This bit is sticky through reset.
0 = Enable LLRB data parity error detection.
1 = Disable LLRB data parity error detection
7 0b
R/W
LLRB Header Parity Error Detect Mask. This bit is sticky through reset.
0 = Enable LLRB header parity error detection.
1 = Disable LLRB header parity error detection
6 0b
R/W
LLRB Control Parity Error Detect Mask. This bit is sticky through reset.
0 = Enable LLRB control parity error detection.
1 = Disable LLRB control parity error detection.
5 0b
R/W
DLLP Timeout Error Detect Mask.
0 = Enable DLLP Timeout error detection.
1 = Disable DLLP Timeout error detection
4:3 00b Reserved
2 0b
R/W
SMB Clock Low Timeout Detect Mask. This bit is sticky through reset.
0 = Enable SMB Clock Low Timeout error detection.
1 = Disable SMB Clock Low Timeout error detection.
1 0b
R/W
Unexpected NAK On SMB Detect Mask. This bit is sticky through reset.
0 = Enable Unexpected NAK on SMB error detection.
1 = Disable Unexpected NAK on SMB error detection.
0 0b
R/W
SMB Lost Bus Arbitration Detect Mask. This bit is sticky through reset.
0 = Enable SMB arbitration loss detection.
1 = Disable SMB arbitration loss detection.