174 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.8.75 EXP_CORERRDMSK – PCI Express Correctable Error
Detect Mask (D2:F0)
Address Offset: 150 – 153h
Access: R/W
Size: 32 Bits
Default: 0000_0000h
The Correctable Error Detect Mask register controls detection of individual errors. An error event
that is masked in this register will not be logged in the Correctable Error Status register, and will
never be reported. There is one mask bit corresponding to every implemented bit in the Correctable
Error Status register. These bits are sticky through reset. This register is specific to the MCH.
3.8.76 EXP_UNITERRDMSK – PCI Express Unit Error Detect Mask
(D2:F0)
Address Offset: 158 – 15Bh
Access: R/W
Size: 32 Bits
Default: 0000_0000h
This register is specific to the MCH, and controls detection of the PCI Express functional unit error
conditions. These bits are sticky through reset.
Bit Field
Default &
Access
Description
31:13 0 Reserved
12 0b
R/W
Replay Timer Timeout Detect Mask. This bit is sticky through system reset.
0 = Detect Replay Timer Timeout error.
1 = Disable Replay Timer timeout error detection.
11:9 0 Reserved
8 0b
R/W
REPLAY_NUM Rollover Error Detect Mask. This bit is sticky through system
reset.
0 = Detect REPLAY_NUM rollover
1 = Disable REPLAY_NUM rollover detection.
7 0b
R/W
Bad DLLP Error Detect Mask. This bit is sticky through system reset.
0 = Detect Bad DLLP error.
1 = Disable Bad DLLP error detection.
6 0b
R/W
Bad TLP Error Detect Mask. OPTIONAL. This bit is sticky through system reset.
0 = Detect Bad TLP error.
1 = Disable Bad TLP error detection.
5:1 0 Reserved
0 0b
R/W
Receiver Error Detect Mask. OPTIONAL. This bit is sticky through system reset.
0 = Detect Receiver error.
1 = Disable Receiver Error error detection.