Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 173
Register Descriptions
3.8.74 EXP_UNCERRDMSK – PCI Express Uncorrectable Error
Detect Mask (D2:F0)
Address Offset: 14C – 14Fh
Access: RO, R/W
Size: 32 Bits
Default: 0000_0000h
The Uncorrectable Error Detect Mask register controls detection of individual errors. An error
event that is masked in this register will not be logged in the Uncorrectable Error Status register,
and will never be reported. There is one mask bit corresponding to every implemented bit in the
Uncorrectable Error Status register. This register is specific to the MCH. These bits are sticky
through reset.
Bit Field
Default &
Access
Description
31:21 000h Reserved
20 0b
R/W
Unsupported Request Error Detect Mask. This bit is sticky through reset.
0 = Detect Unsupported Request Error
1 = Disable Unsupported Request Error detection
19 0b
RO
ECRC Error Detect Mask. OPTIONAL. Not implemented.
18 0b
R/W
Malformed TLP Detect Mask. This bit is sticky through reset.
0 = Detect Malformed TLP Error
1 = Disable Malformed TLP Error detection
17 0b
R/W
Receiver Overflow Detect Mask. This bit is sticky through reset. OPTIONAL
0 = Detect Receiver Overflow Error
1 = Disable Receiver Overflow Error detection
16 0b
R/W
Unexpected Completion Detect Mask. This bit is sticky through reset.
0 = Detect Unexpected Completion Error
1 = Disable Unexpected Completion Error detection
15 0b
R/W
Completer Abort Detect Mask. This bit is sticky through reset. OPTIONAL
0 = Detect Completer Abort Error
1 = Disable Completer Abort Error detection
14 0b
R/W
Completion Timeout Detect Mask. This bit is sticky through reset.
0 = Detect Completion Timeout Error
1 = Disable Completion Timeout Error detection
13 0b
R/W
Flow Control Protocol Error Detect Mask. This bit is sticky through reset.
OPTIONAL
0 = Detect Flow Control Protocol Error
1 = Disable Flow Control Protocol Error detection
12 0b
R/W
Poisoned TLP Detect Mask. This bit is sticky through reset.
0 = Detect Poisoned TLP Error
1 = Disable Poisoned TLP Error detection
11:5 0 Reserved
4 0b
R/W
Data Link Protocol Error Detect Mask. This bit is sticky through reset.
0 = Detect Data Link Protocol Error
1 = Disable Data Link Protocol Error detection
3:1 0 Reserved
0 0b
R/O
Training Error Detect Mask. Not Implemented.
