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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
172 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
Bit Field
Default &
Access
Description
31:29 000b Reserved
28:24 0_0000b
RO
First Error Pointer for Unmasked PCI Express Correctable Errors. This
pointer is rearmed when all unmasked errors have been cleared. In the event of
simultaneous errors, the pointer indicates the least significant bit of the group.
These bits are sticky.
23:21 000b Reserved
20:16 0_0000b
R/W
First Error Pointer for PCI Express unit errors. This pointer is locked once any
units errors are logged in the EXP_FERR. It is rearmed when all EXP_unit errors
have been cleared. In the event of simultaneous errors, the pointer indicates the
least significant bit of the group. This pointer is only valid for an error that is
enabled for reporting. These bits are sticky.
15 0b
R/W
Enable Header Log Use for LLE Protocol Error. The header log is used by PCI
Express uncorrectable errors. This feature is used to capture the header log for
the LLE protocol error in the unit error register during debug.
14 0b
R/W
PCI Express Unit Report Enable. This bit enables reporting of fatal, non-fatal
and correctable unit errors.
0 = Disable
1 = Enable
13:12 00b
R/W
Fatal Unit Error Report Steering. Selects the method of reporting fatal errors if
unit error reporting is enabled (bit 14).
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
11:10 00b
R/W
Non-Fatal Unit Error Report Steering. Selects the method of reporting non-fatal
errors if unit error reporting is enabled (bit 14).
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
9:8 00b
R/W
Correctable Unit Error Report Steering. Selects the method of reporting
correctable errors if unit error reporting is enabled (bit 14).
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
7:6 00b Reserved
5:4 00b
R/W
Fatal Root Port Error Report Steering. Selects the method of reporting a fatal
error in any of the devices in the hierarchy associated with this root port (internally
detected or via a message received on the link). This functionality is enabled via
EXP_RPCTL[2].
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
3:2 00b
R/W
Nonfatal Root Port Error Report Steering. Selects the method of reporting a
non-fatal error in any of the devices in the hierarchy associated with this root port
(internally detected or via a message received on the link). This functionality is
enabled via EXP_RPCTL[1].
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
1:0 00b
R/W
Correctable Root Port Error Report Steering. Selects the method of reporting a
correctable error in any of the devices in the hierarchy associated with this root
port (internally detected or via a message received on the link). This functionality
is enabled via EXP_RPCTL[0].
00b = SCI 10b = SERR
01b = SMI 11b = MCERR
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