Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 171
Register Descriptions
3.8.73 EXP_ERRDOCMD – PCI Express Error Do Command
Register (D2:F0)
Address Offset: 148 – 14Bh
Access: RO, R/W
Size: 32 Bits
Default: 0000_0000h
This register supports PCI Express error signaling commands. DO_SCI, DO_SMI, and
DO_MCERR, DO_SERR must further be enabled by the PCI Express Host Do Command register.
11 0b
R/W
Link Down Error Mask. Mask reporting of detected link transitions from DL_UP
to DL_DOWN. This bit is sticky through reset.
0 = Enable link down error mask reporting.
1 = Disable link down error mask reporting.
10 0b
R/W
Downstream Data Queue Parity Error Reporting Mask. This bit is sticky through
reset.
0 = Enable
1 = Disable
9 0b
R/W
LUT Parity Error Reporting Mask. This bit is sticky through reset.
0 = Enable LUT parity error reporting.
1 = Disable LUT parity error reporting.
8 0b
R/W
LLRB Data Parity Error Reporting Mask. This bit is sticky through reset.
0 = Enable LLRB data parity error reporting.
1 = Disable LLRB data parity error reporting.
7 0b
R/W
LLRB Header Parity Error Reporting Mask. This bit is sticky through reset.
0 = Enable LLRB header parity error reporting.
1 = Disable LLRB header parity error reporting.
6 0b
R/W
LLRB Control Parity Error Reporting Mask. This bit is sticky through reset.
0 = Enable LLRB control parity error reporting.
1 = Disable LLRB control parity error reporting.
5 0b
R/W
DLLP Timeout Error Reporting Mask. This bit is sticky through reset.
0 = Enable DLLP timeout error reporting.
1 = Disable DLLP timeout error reporting.
4:3 00b Reserved
2 0b
R/W
SMBCLTO Reporting Mask. This bit is sticky through reset.
0 = Enable SMBCLTO reporting.
1 = Disable SMBCLTO reporting.
1 0b
R/W
UESMBN Reporting Mask. This bit is sticky through reset.
0 = Enable UESMBN reporting.
1 = Disable UESMBN reporting.
0 0b
R/W
SMBLA Reporting Mask. This bit is sticky through reset.
0 = Enable SMBLA reporting.
1 = Disable SMBLA reporting.
Bit Field
Default &
Access
Description